summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/haswell/romstage.c38
1 files changed, 19 insertions, 19 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index dfadad24aa..39babf5336 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -46,25 +46,25 @@ void mainboard_romstage_entry(void)
int wake_from_s3;
struct pei_data pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = get_pch_platform_type(),
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .ec_present = cfg->ec_present,
- .gbe_enable = gbe && gbe->enabled,
- .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
- .dq_pins_interleaved = cfg->dq_pins_interleaved,
- .max_ddr3_freq = 1600,
- .usb_xhci_on_resume = cfg->usb_xhci_on_resume,
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .hpet_address = HPET_ADDR,
+ .rcba = (uintptr_t)DEFAULT_RCBA,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .temp_mmio_base = 0xfed08000,
+ .system_type = get_pch_platform_type(),
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .ec_present = cfg->ec_present,
+ .gbe_enable = gbe && gbe->enabled,
+ .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
+ .dq_pins_interleaved = cfg->dq_pins_interleaved,
+ .max_ddr3_freq = 1600,
+ .usb_xhci_on_resume = cfg->usb_xhci_on_resume,
};
mainboard_fill_pei_data(&pei_data);