3 files changed, 59 insertions, 0 deletions

diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index 4a5ed4f687..6d2b4f4759 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -20,6 +20,20 @@
 #include <soc/clock.h>
 #include <soc/grf.h>
 
+static void configure_emmc(void)
+{
+	/* Host controller does not support programmable clock generator.
+	 * If we don't do this setting, when we use phy to control the
+	 * emmc clock(when clock exceed 50MHz), it will get wrong clock.
+	 *
+	 * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
+	 * Please search "_CON11[7:0]" to locate register description.
+	 */
+	write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
+
+	rkclk_configure_emmc();
+}
+
 static void configure_sdmmc(void)
 {
 	gpio_output(GPIO(4, D, 5), 1);  /* SDMMC_PWR_EN */
@@ -72,6 +86,7 @@ static void configure_sdmmc(void)
 static void mainboard_init(device_t dev)
 {
 	configure_sdmmc();
+	configure_emmc();
 }
 
 static void mainboard_enable(device_t dev)
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 53c6e30e5b..6222b77730 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -133,6 +133,20 @@ enum {
 	ACLK_PERIHP_DIV_CON_MASK	= 0x1f,
 	ACLK_PERIHP_DIV_CON_SHIFT	= 0,
 
+	/* CLKSEL_CON21 */
+	ACLK_EMMC_PLL_SEL_MASK          = 0x1,
+	ACLK_EMMC_PLL_SEL_SHIFT         = 7,
+	ACLK_EMMC_PLL_SEL_GPLL          = 0x1,
+	ACLK_EMMC_DIV_CON_MASK          = 0x1f,
+	ACLK_EMMC_DIV_CON_SHIFT         = 0,
+
+	/* CLKSEL_CON22 */
+	CLK_EMMC_PLL_MASK               = 0x7,
+	CLK_EMMC_PLL_SHIFT              = 8,
+	CLK_EMMC_PLL_SEL_GPLL           = 0x1,
+	CLK_EMMC_DIV_CON_MASK           = 0x7f,
+	CLK_EMMC_DIV_CON_SHIFT          = 0,
+
 	/* CLKSEL_CON23 */
 	PCLK_PERILP0_DIV_CON_MASK	= 0x7,
 	PCLK_PERILP0_DIV_CON_SHIFT	= 12,
@@ -736,3 +750,32 @@ void rkclk_configure_tsadc(unsigned int hz)
 			src_clk_div << CLK_TSADC_DIV_CON_SHIFT |
 			CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT));
 }
+
+void rkclk_configure_emmc(void)
+{
+	int src_clk_div;
+	int aclk_emmc = 198*MHz;
+	int clk_emmc = 198*MHz;
+
+	/* Select aclk_emmc source from GPLL */
+	src_clk_div = GPLL_HZ / aclk_emmc;
+	assert((src_clk_div - 1 < 31) && (src_clk_div * aclk_emmc == GPLL_HZ));
+
+	write32(&cru_ptr->clksel_con[21],
+		RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK <<
+						ACLK_EMMC_PLL_SEL_SHIFT |
+			      ACLK_EMMC_DIV_CON_MASK << ACLK_EMMC_DIV_CON_SHIFT,
+			      ACLK_EMMC_PLL_SEL_GPLL <<
+						ACLK_EMMC_PLL_SEL_SHIFT |
+			      (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT));
+
+	/* Select clk_emmc source from GPLL too */
+	src_clk_div = GPLL_HZ / clk_emmc;
+	assert((src_clk_div - 1 < 127) && (src_clk_div * clk_emmc == GPLL_HZ));
+
+	write32(&cru_ptr->clksel_con[22],
+		RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT |
+			      CLK_EMMC_DIV_CON_MASK << CLK_EMMC_DIV_CON_SHIFT,
+			      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
+			      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT));
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index 3b60d547cf..286abec06f 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -106,6 +106,7 @@ void rkclk_init(void);
 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz);
 void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
 void rkclk_configure_ddr(unsigned int hz);
+void rkclk_configure_emmc(void);
 void rkclk_configure_saradc(unsigned int hz);
 void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 void rkclk_configure_tsadc(unsigned int hz);