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-rw-r--r--src/mainboard/msi/ms6178/Options.lb11
-rw-r--r--src/northbridge/intel/i82810/northbridge.c2
2 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb
index 07c1a10770..8ccd8683e1 100644
--- a/src/mainboard/msi/ms6178/Options.lb
+++ b/src/mainboard/msi/ms6178/Options.lb
@@ -65,6 +65,7 @@ uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
+uses HAVE_HIGH_TABLES
default ROM_SIZE = 512 * 1024
default HAVE_FALLBACK_BOOT = 1
@@ -75,7 +76,7 @@ default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb.
default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
+default FALLBACK_SIZE = ROM_IMAGE_SIZE
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 16 * 1024
default HAVE_OPTION_TABLE = 0
@@ -96,10 +97,6 @@ default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default CONFIG_CONSOLE_VGA = 1
default CONFIG_PCI_ROM_RUN = 1
-
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=0
+default CONFIG_CBFS = 1
+default HAVE_HIGH_TABLES = 1
end
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index bfbd338069..40c8ee0e69 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -170,7 +170,7 @@ static void pci_domain_set_resources(device_t dev)
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 1024, tolmk - 1024);
+ ram_resource(dev, idx++, 768, tolmk - 768);
#if HAVE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */