diff options
Diffstat (limited to 'targets/iwill/dk8x/Config.lb')
| -rw-r--r-- | targets/iwill/dk8x/Config.lb | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/targets/iwill/dk8x/Config.lb b/targets/iwill/dk8x/Config.lb index bcb18b8998..ab4ff09c60 100644 --- a/targets/iwill/dk8x/Config.lb +++ b/targets/iwill/dk8x/Config.lb @@ -6,13 +6,13 @@ target dk8x mainboard iwill/dk8x -option HAVE_HARD_RESET=1 +option CONFIG_HAVE_HARD_RESET=1 -option HAVE_OPTION_TABLE=1 -option HAVE_MP_TABLE=1 -option ROM_SIZE=1024*1024 +option CONFIG_HAVE_OPTION_TABLE=1 +option CONFIG_HAVE_MP_TABLE=1 +option CONFIG_ROM_SIZE=1024*1024 -option HAVE_FALLBACK_BOOT=1 +option CONFIG_HAVE_FALLBACK_BOOT=1 #option CONFIG_LSI_SCSI_FW_FIXUP=1 @@ -21,8 +21,8 @@ option HAVE_FALLBACK_BOOT=1 ### ### Build code to export a programmable irq routing table ### -option HAVE_PIRQ_TABLE=1 -option IRQ_SLOT_COUNT=12 +option CONFIG_HAVE_PIRQ_TABLE=1 +option CONFIG_IRQ_SLOT_COUNT=12 # ### ### Build code for SMP support @@ -39,7 +39,7 @@ option CONFIG_MAX_PHYSICAL_CPUS=2 option CONFIG_IOAPIC=1 # ### -### MEMORY_HOLE instructs earlymtrr.inc to +### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to ### enable caching from 0-640KB and to disable ### caching from 640KB-1MB using fixed MTRRs ### @@ -47,24 +47,24 @@ option CONFIG_IOAPIC=1 ### CPU identification depends on only variable MTRRs ### being enabled. ### -#option MEMORY_HOLE=0 +#option CONFIG_MEMORY_HOLE=0 # ### ### Clean up the motherboard id strings ### -option MAINBOARD_PART_NUMBER="DK8X" -option MAINBOARD_VENDOR="IWILL" +option CONFIG_MAINBOARD_PART_NUMBER="DK8X" +option CONFIG_MAINBOARD_VENDOR="IWILL" # ### ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -#option FALLBACK_SIZE=524288 -#option FALLBACK_SIZE=98304 -option FALLBACK_SIZE=131072 +#option CONFIG_FALLBACK_SIZE=524288 +#option CONFIG_FALLBACK_SIZE=98304 +option CONFIG_FALLBACK_SIZE=131072 -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -option ROM_IMAGE_SIZE=65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +option CONFIG_ROM_IMAGE_SIZE=65536 ### @@ -77,7 +77,7 @@ option ROM_IMAGE_SIZE=65536 #option CONFIG_COMPRESS=1 option CONFIG_CONSOLE_SERIAL8250=1 -option TTYS0_BAUD=115200 +option CONFIG_TTYS0_BAUD=115200 ## ### Select the coreboot loglevel @@ -89,30 +89,30 @@ option TTYS0_BAUD=115200 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -option DEFAULT_CONSOLE_LOGLEVEL=7 +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 ## At a maximum only compile in this level of debugging -option MAXIMUM_CONSOLE_LOGLEVEL=7 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7 -#option DEBUG=1 +#option CONFIG_DEBUG=1 # ## Coreboot C code runs at this location in RAM -option _RAMBASE=0x004000 +option CONFIG_RAMBASE=0x004000 ## ## Use a 32K stack ## -option STACK_SIZE=0x8000 +option CONFIG_STACK_SIZE=0x8000 ## ## Use a 56K heap ## -option HEAP_SIZE=0xe000 +option CONFIG_HEAP_SIZE=0xe000 # ### @@ -125,22 +125,22 @@ option CONFIG_ROM_PAYLOAD = 1 # romimage "normal" # 48K for SCSI FW -# option ROM_SIZE = 512*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024 # 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" - option USE_FALLBACK_IMAGE=0 - option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) - option ROM_SECTION_OFFSET= 0 + option CONFIG_USE_FALLBACK_IMAGE=0 + option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) + option CONFIG_ROM_SECTION_OFFSET= 0 - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) + option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) + option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 +# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) + option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) payload /usr/src/filo-0.4.1_btext/filo.elf # payload /usr/src/filo-0.4.2/filo.elf @@ -148,20 +148,20 @@ end romimage "fallback" option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_SECTION_SIZE = FALLBACK_SIZE - option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE) + option CONFIG_USE_FALLBACK_IMAGE=1 + option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) - option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - option _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) + option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) + option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) + option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) -# option XIP_ROM_SIZE = FALLBACK_SIZE - option XIP_ROM_SIZE = 65536 - option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +# option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE + option CONFIG_XIP_ROM_SIZE = 65536 + option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) payload ../../../payloads/filo.elf # payload /usr/src/filo-0.4.2/filo.elf end -buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" |