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-rw-r--r--targets/jetway/j7f24/Config.lb12
1 files changed, 6 insertions, 6 deletions
diff --git a/targets/jetway/j7f24/Config.lb b/targets/jetway/j7f24/Config.lb
index 268873d07a..52a1108ee3 100644
--- a/targets/jetway/j7f24/Config.lb
+++ b/targets/jetway/j7f24/Config.lb
@@ -22,24 +22,24 @@
target jetway-j7f24
mainboard jetway/j7f24
-option MAXIMUM_CONSOLE_LOGLEVEL=8
-option DEFAULT_CONSOLE_LOGLEVEL=8
+option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
# coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
+option CONFIG_RAMBASE=0x00004000
#
# If space is allotted for a VGA BIOS,
# generate the final ROM like this:
# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
#
-#option ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
-option ROM_SIZE = (512 * 1024)
+#option CONFIG_ROM_SIZE = (512 * 1024) - (63 * 1024) - (64 * 1024)
+option CONFIG_ROM_SIZE = (512 * 1024)
romimage "image"
option COREBOOT_EXTRA_VERSION = "-j7f24"
payload ../payload.elf
end
-buildrom ./coreboot.rom ROM_SIZE "image"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"