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-rw-r--r--targets/totalimpact/briq/Config.lb32
1 files changed, 16 insertions, 16 deletions
diff --git a/targets/totalimpact/briq/Config.lb b/targets/totalimpact/briq/Config.lb
index 92288234fe..c352936ba4 100644
--- a/targets/totalimpact/briq/Config.lb
+++ b/targets/totalimpact/briq/Config.lb
@@ -12,47 +12,47 @@ option CONFIG_USE_INIT=1
option CONFIG_COMPRESS=0
## Turn off POST codes
-option NO_POST=1
+option CONFIG_NO_POST=1
## Enable serial console
-option DEFAULT_CONSOLE_LOGLEVEL=8
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
## Boot linux from IDE
option CONFIG_IDE_PAYLOAD=1
-option IDE_BOOT_DRIVE=0
-option IDE_SWAB=1
-option IDE_OFFSET=0
+option CONFIG_IDE_BOOT_DRIVE=0
+option CONFIG_IDE_SWAB=1
+option CONFIG_IDE_OFFSET=0
# ROM is 1Mb
-option ROM_SIZE=1024*1024
+option CONFIG_ROM_SIZE=1024*1024
# Set stack and heap sizes (stage 2)
-option STACK_SIZE=0x10000
-option HEAP_SIZE=0x10000
+option CONFIG_STACK_SIZE=0x10000
+option CONFIG_HEAP_SIZE=0x10000
# Sandpoint Demo Board
romimage "normal"
## Base of ROM
- option _ROMBASE=0xfff00000
+ option CONFIG_ROMBASE=0xfff00000
## Sandpoint reset vector
- option _RESET=_ROMBASE+0x100
+ option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
- option _EXCEPTION_VECTORS=_RESET+0x100
+ option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
- ## = _RESET + exeception vector table size
- option _ROMSTART=_RESET+0x3100
+ ## = CONFIG_RESET + exeception vector table size
+ option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
- option _RAMBASE=0x00100000
- option _RAMSTART=0x00100000
+ option CONFIG_RAMBASE=0x00100000
+ option CONFIG_RAMSTART=0x00100000
option CONFIG_BRIQ_750FX=1
#option CONFIG_BRIQ_7400=1
end
-buildrom ./coreboot.rom ROM_SIZE "normal"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal"