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path: root/util/msrtool/intel_core1.c
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Diffstat (limited to 'util/msrtool/intel_core1.c')
-rw-r--r--util/msrtool/intel_core1.c128
1 files changed, 64 insertions, 64 deletions
diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c
index 1848698d46..fdf4005cc8 100644
--- a/util/msrtool/intel_core1.c
+++ b/util/msrtool/intel_core1.c
@@ -22,196 +22,196 @@ int intel_core1_probe(const struct targetdef *target, const struct cpuid_t *id)
}
const struct msrdef intel_core1_msrs[] = {
- {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+ {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", {
{ BITS_EOT }
}},
- {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
+ {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", {
{ BITS_EOT }
}},
- {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", {
+ {0xcd, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_STS", "", {
{ BITS_EOT }
}},
- {0xce, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_VCC", "", {
+ {0xce, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_VCC", "", {
{ BITS_EOT }
}},
- {0xe2, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_CST_CONFIG_CONTROL", "", {
+ {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_CST_CONFIG_CONTROL", "", {
{ BITS_EOT }
}},
- {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", {
+ {0xe3, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_BASE_ADDR", "", {
{ BITS_EOT }
}},
- {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", {
+ {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_CAPTURE_ADDR", "", {
{ BITS_EOT }
}},
- {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", {
+ {0xee, MSRTYPE_RDWR, MSR2(0, 0), "EXT_CONFIG", "", {
{ BITS_EOT }
}},
- {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
+ {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", {
{ BITS_EOT }
}},
- {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", {
+ {0x194, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_FLEX_MAX", "", {
{ BITS_EOT }
}},
- {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+ {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", {
{ BITS_EOT }
}},
- {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
+ {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", {
{ BITS_EOT }
}},
- {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", {
+ {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "PIC_SENS_CFG", "", {
{ BITS_EOT }
}},
- {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+ {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", {
{ BITS_EOT }
}},
- {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+ {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", {
{ BITS_EOT }
}},
- {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+ {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
- {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+ {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", {
{ BITS_EOT }
}},
- {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+ {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", {
{ BITS_EOT }
}},
- {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
+ {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", {
{ BITS_EOT }
}},
- {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", {
+ {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TEMPERATURE_OFFSET", "", {
{ BITS_EOT }
}},
- {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+ {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", {
{ BITS_EOT }
}},
- {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
+ {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", {
{ BITS_EOT }
}},
- {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
+ {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", {
{ BITS_EOT }
}},
- {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
+ {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", {
{ BITS_EOT }
}},
- {0x15f, MSRTYPE_RDWR, MSR2(0,0), "DTS_CAL_CTRL", "", {
+ {0x15f, MSRTYPE_RDWR, MSR2(0, 0), "DTS_CAL_CTRL", "", {
{ BITS_EOT }
}},
- {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+ {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", {
{ BITS_EOT }
}},
- {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+ {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", {
{ BITS_EOT }
}},
- {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
+ {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", {
{ BITS_EOT }
}},
- {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+ {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", {
{ BITS_EOT }
}},
- {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
+ {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", {
{ BITS_EOT }
}},
- {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
+ {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", {
{ BITS_EOT }
}},
- {0x19d, MSRTYPE_RDWR, MSR2(0,0), "GV_THERM", "", {
+ {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "GV_THERM", "", {
{ BITS_EOT }
}},
- {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+ {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", {
{ BITS_EOT }
}},
- {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+ {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", {
{ BITS_EOT }
}},
- {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+ {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", {
{ BITS_EOT }
}},
- {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+ {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", {
{ BITS_EOT }
}},
- {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+ {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", {
{ BITS_EOT }
}},
- {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+ {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", {
{ BITS_EOT }
}},
- {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+ {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", {
{ BITS_EOT }
}},
- {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+ {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", {
{ BITS_EOT }
}},
- {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+ {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", {
{ BITS_EOT }
}},
- {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+ {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", {
{ BITS_EOT }
}},
- {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+ {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", {
{ BITS_EOT }
}},
- {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+ {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", {
{ BITS_EOT }
}},
- {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+ {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", {
{ BITS_EOT }
}},
- {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+ {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", {
{ BITS_EOT }
}},
- {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+ {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", {
{ BITS_EOT }
}},
- {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+ {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", {
{ BITS_EOT }
}},
- {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+ {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", {
{ BITS_EOT }
}},
- {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+ {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", {
{ BITS_EOT }
}},
- {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+ {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", {
{ BITS_EOT }
}},
- {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+ {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", {
{ BITS_EOT }
}},
- {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+ {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", {
{ BITS_EOT }
}},
- {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+ {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", {
{ BITS_EOT }
}},
- {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+ {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", {
{ BITS_EOT }
}},
- {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+ {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", {
{ BITS_EOT }
}},
- {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+ {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", {
{ BITS_EOT }
}},
- {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+ {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", {
{ BITS_EOT }
}},
- {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+ {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", {
{ BITS_EOT }
}},
- {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+ {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", {
{ BITS_EOT }
}},
- {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+ {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", {
{ BITS_EOT }
}},
{ MSR_EOT }
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 16:13:06 +0000