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-rw-r--r--util/romcc/tests/linux_test2.c6
-rw-r--r--util/romcc/tests/raminit_test.c4
-rw-r--r--util/romcc/tests/raminit_test1.c4
-rw-r--r--util/romcc/tests/raminit_test2.c4
-rw-r--r--util/romcc/tests/simple_test30.c6
5 files changed, 12 insertions, 12 deletions
diff --git a/util/romcc/tests/linux_test2.c b/util/romcc/tests/linux_test2.c
index 577e0c3c2a..c4fbf0a238 100644
--- a/util/romcc/tests/linux_test2.c
+++ b/util/romcc/tests/linux_test2.c
@@ -155,8 +155,8 @@ static void setup_coherent_ht_domain(void)
* 0 = No coherent HT configuration space restrictions
* 1 = Limit coherent HT configuration space based on node count
* [16:16] Local Interrupt Conversion Enable.
- * 0 = ExtInt/NMI interrups unaffected.
- * 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
+ * 0 = ExtInt/NMI interrupts unaffected.
+ * 1 = ExtInt/NMI broadcast interrupts converted to LINT0/1
* [17:17] APIC Extended Broadcast Enable.
* 0 = APIC broadcast is 0F
* 1 = APIC broadcast is FF
@@ -484,7 +484,7 @@ static void setup_coherent_ht_domain(void)
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c
index b1baf7e49d..564786b51c 100644
--- a/util/romcc/tests/raminit_test.c
+++ b/util/romcc/tests/raminit_test.c
@@ -754,7 +754,7 @@ static void spd_set_dramc(void)
{
/*
* Effects: Uses serial presence detect to set the
- * DRAMC register, which records if ram is registerd or not,
+ * DRAMC register, which records if ram is registered or not,
* and controls the refresh rate.
* The refresh rate is not set here, as memory refresh
* cannot be enbaled until after memory is initialized.
@@ -997,7 +997,7 @@ static void spd_set_nbxcfg(void)
}
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg);
/* Now see if reg is 0xff. If it is we are done. If not,
- * we need to set 0x18 into regster 0x50.l
+ * we need to set 0x18 into register 0x50.l
* we will do this in two steps, first or in 0x80 to 0x50.b,
* then or in 0x1 to 0x51.b
*/
diff --git a/util/romcc/tests/raminit_test1.c b/util/romcc/tests/raminit_test1.c
index b1baf7e49d..564786b51c 100644
--- a/util/romcc/tests/raminit_test1.c
+++ b/util/romcc/tests/raminit_test1.c
@@ -754,7 +754,7 @@ static void spd_set_dramc(void)
{
/*
* Effects: Uses serial presence detect to set the
- * DRAMC register, which records if ram is registerd or not,
+ * DRAMC register, which records if ram is registered or not,
* and controls the refresh rate.
* The refresh rate is not set here, as memory refresh
* cannot be enbaled until after memory is initialized.
@@ -997,7 +997,7 @@ static void spd_set_nbxcfg(void)
}
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg);
/* Now see if reg is 0xff. If it is we are done. If not,
- * we need to set 0x18 into regster 0x50.l
+ * we need to set 0x18 into register 0x50.l
* we will do this in two steps, first or in 0x80 to 0x50.b,
* then or in 0x1 to 0x51.b
*/
diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c
index c5b366ff5a..af6eaaef88 100644
--- a/util/romcc/tests/raminit_test2.c
+++ b/util/romcc/tests/raminit_test2.c
@@ -754,7 +754,7 @@ static void spd_set_dramc(void)
{
/*
* Effects: Uses serial presence detect to set the
- * DRAMC register, which records if ram is registerd or not,
+ * DRAMC register, which records if ram is registered or not,
* and controls the refresh rate.
* The refresh rate is not set here, as memory refresh
* cannot be enbaled until after memory is initialized.
@@ -997,7 +997,7 @@ static void spd_set_nbxcfg(void)
}
pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg);
/* Now see if reg is 0xff. If it is we are done. If not,
- * we need to set 0x18 into regster 0x50.l
+ * we need to set 0x18 into register 0x50.l
* we will do this in two steps, first or in 0x80 to 0x50.b,
* then or in 0x1 to 0x51.b
*/
diff --git a/util/romcc/tests/simple_test30.c b/util/romcc/tests/simple_test30.c
index ede20917d9..6130ca7b64 100644
--- a/util/romcc/tests/simple_test30.c
+++ b/util/romcc/tests/simple_test30.c
@@ -569,8 +569,8 @@ static void setup_coherent_ht_domain(void)
* 0 = No coherent HT configuration space restrictions
* 1 = Limit coherent HT configuration space based on node count
* [16:16] Local Interrupt Conversion Enable.
- * 0 = ExtInt/NMI interrups unaffected.
- * 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
+ * 0 = ExtInt/NMI interrupts unaffected.
+ * 1 = ExtInt/NMI broadcast interrupts converted to LINT0/1
* [17:17] APIC Extended Broadcast Enable.
* 0 = APIC broadcast is 0F
* 1 = APIC broadcast is FF
@@ -898,7 +898,7 @@ static void setup_coherent_ht_domain(void)
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,