3 files changed, 212 insertions, 0 deletions
diff --git a/util/inteltools/Makefile b/util/inteltools/Makefile
new file mode 100644
index 0000000000..f7a5b324d2
--- /dev/null
+++ b/util/inteltools/Makefile
@@ -0,0 +1,62 @@
+#
+# Makefile for ich_gpio utility
+# 
+# (C) 2008 by coresystems GmbH
+# written by Stefan Reinauer <stepan@coresystems.de>
+# Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
+#
+
+PROGRAM = ich_gpio
+
+CC = gcc
+STRIP	= strip
+INSTALL = /usr/bin/install
+PREFIX = /usr/local
+CFLAGS = -O2 -g -Wall
+OS_ARCH = $(shell uname)
+ifeq ($(OS_ARCH), SunOS)
+LDFLAGS = -lpci -lz
+else
+LDFLAGS = -lpci -lz -static 
+STRIP_ARGS = -s
+endif
+
+OBJS = ich_gpio.o
+
+all: pciutils dep $(PROGRAM)
+
+$(PROGRAM): $(OBJS)
+	$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
+	$(STRIP) $(STRIP_ARGS) $(PROGRAM)
+
+clean:
+	rm -f *.o *~
+
+distclean: clean
+	rm -f $(PROGRAM) .dependencies
+	
+dep:
+	@$(CC) -MM *.c > .dependencies
+
+pciutils:
+	@echo; echo -n "Checking for pciutils and zlib... "
+	@$(shell ( echo "#include <pci/pci.h>";		   \
+		   echo "struct pci_access *pacc;";	   \
+		   echo "int main(int argc, char **argv)"; \
+		   echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c )
+	@$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null &&	\
+		echo "found." || ( echo "not found."; echo;		\
+		echo "Please install pciutils-devel and zlib-devel.";	\
+		echo "See README for more information."; echo;		\
+		rm -f .test.c .test; exit 1)
+	@rm -f .test.c .test
+
+install: $(PROGRAM)
+	$(INSTALL) $(PROGRAM) $(PREFIX)/sbin
+	mkdir -p $(PREFIX)/share/man/man8
+	$(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8
+
+.PHONY: all clean distclean dep pciutils
+
+-include .dependencies
+
diff --git a/util/inteltools/ich_gpio.8 b/util/inteltools/ich_gpio.8
new file mode 100644
index 0000000000..17ae80595f
--- /dev/null
+++ b/util/inteltools/ich_gpio.8
@@ -0,0 +1,59 @@
+.TH ICH_GPIO 8 "March 8, 2008"
+.SH NAME
+ich_gpio \- Intel southbridge GPIO Dump Utility
+.SH SYNOPSIS
+.B ich_gpio
+.SH DESCRIPTION
+.B ich_gpio 
+is a user-space utility which can dump all 
+register contents of the Intel ICH series Southbridges.
+.PP
+It is mainly used for coreboot development purposes (see coreboot.org
+for details on coreboot), but it may also be useful for other things.
+.PP
+Here is an example output:
+.br
+[root@localhost dumpgpio]# ich_gpio
+.br
+Intel Southbridge: 8086:24c0
+.br
+GPIOBASE = 0x0500
+.br
+gpiobase+0x0000: 0x1a003180
+.br
+gpiobase+0x0004: 0x0900ffff
+.br
+gpiobase+0x0008: 0x00000000
+.br
+gpiobase+0x000c: 0x1bbf0000
+.br
+gpiobase+0x0010: 0x00000000
+.br
+gpiobase+0x0014: 0x00000000
+.br
+gpiobase+0x0018: 0x00040000
+.br
+gpiobase+0x001c: 0x00000000
+.br
+gpiobase+0x0020: 0x00000000
+.br
+gpiobase+0x0024: 0x00000000
+.br
+gpiobase+0x0028: 0x00000000
+.br
+gpiobase+0x002c: 0x00003000
+.br
+gpiobase+0x0030: 0x00000fff
+.br
+gpiobase+0x0034: 0x00000e00
+.br
+gpiobase+0x0038: 0x00000fff
+.br
+gpiobase+0x003c: 0x00000000
+.PP
+Please consult your datasheet for the register meanings.
+.SH OPTIONS
+No command line options needed just run ich_gpio.
+.SH AUTHORS
+Please see the individual source code files.
+
diff --git a/util/inteltools/ich_gpio.c b/util/inteltools/ich_gpio.c
new file mode 100644
index 0000000000..39e3dbcad7
--- /dev/null
+++ b/util/inteltools/ich_gpio.c
@@ -0,0 +1,91 @@
+/*
+ * dump gpio on intel ICH series southbridges
+ *
+ * Copyright (C) 2008 by coresystems GmbH 
+ * written by Stefan Reinauer <stepan@coresystems.de> 
+ * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <getopt.h>
+
+#include <sys/io.h>
+#include <pci/pci.h>
+
+int map_gpio(uint16_t gpio)
+{
+	int i;
+	unsigned long size=0x40;
+
+	for (i=0; i<size; i+=4) {
+		printf("gpiobase+0x%04x: 0x%08x\n", i, inl(gpio+i));
+	}
+
+	return 0;
+}
+
+int main(int argc, char *argv[])
+{
+	struct pci_access *pacc;
+	struct pci_dev *sb;
+	uint16_t gpiobadd;
+	uint16_t device;
+
+	if (iopl(3)) { 
+		perror("You need to be root.\n"); 
+		exit(1);
+	}
+
+	pacc = pci_alloc();
+	pci_init(pacc);
+	pci_scan_bus(pacc);
+
+	sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
+	if (!sb) {
+		printf("No southbridge found.\n");
+		exit(1);
+	}
+
+	if (pci_read_word(sb, 0) != 0x8086) {
+		printf("Not an Intel southbridge.\n");
+		exit(1);
+	}
+
+	printf("Intel Southbridge: %04x:%04x\n", 
+		pci_read_word(sb, 0), pci_read_word(sb, 2));
+
+	device = pci_read_word(sb, 2);
+
+	if (device < 0x2640) {
+		gpiobadd = pci_read_word(sb, 0x58) & 0xfffc; 
+	} else if (device >= 0x2640) {
+		gpiobadd = pci_read_word(sb, 0x48) & 0xfffc;
+	}
+	printf("GPIOBASE = 0x%04x\n\n", gpiobadd);
+
+	map_gpio(gpiobadd);
+
+
+	return 0;
+}