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The 3 commits commits from the blob repository this patch pulls in
remove executable flags from files in the repo that shouldn't have those
flags set:
* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit
* Remove execute permission from all binaries
* Remove execute permission from plaintext files
Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This pulls in the following changes:
* soc/intel/baytrail/microcode.bin: Remove outdated microcode
* mainboard/amd/mandolin: add Cereme APCB
Change-Id: If6dd7881b346782635dec07710fe5c4449254e3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Changes in 3rdparty/blobs:
* Update of the OCP Tiogapass Flash descriptor binary
* Move binary policy as README.md
* Markdownify README.md
* Add APCB binary for AMD Mandolin
Change-Id: I0c45969626f30dca42bba1f137e85ec0999fc671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I5f053c1270bab71aeab3bb785c60417419736b44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Upgrade to blobs version with descriptor and Intel ME binary
BUG=N/A
TEST=booting Facebook FBG1701
Change-Id: I2143b94a81eebfb22d99833aaf1f3743983dd80c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34442
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the 3rdparty/blobs submodule to the newest HEAD, which
contains the SPM binary for MT8183 platforms
( https://review.coreboot.org/c/blobs/+/34543 ).
Change-Id: I505ec9fffd9ddd62fffbe9514cbba50625825693
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34734
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Uprev the 3rdparty/blobs submodule to the newest HEAD, which
contains the SSPM binary for MT8183 platforms
( https://review.coreboot.org/c/blobs/+/32698 ).
Change-Id: I8a4dfa7eaace1ea473f5970596c3201342e48927
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34494
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The sandybridge systemagent-r6 blob is modified:
- To be more flexible about the location of the stack w.r.t. the heap
- Place the MRC pool right below the MRC_VAR region
- to work with the same DCACHE_RAM_BASE from the native raminit (could
make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native
bootpath and also allows for BIOS/memory mappeds region larger than
8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also
include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Update SMU firmware for amd/stoneyridge
* Remove stale Sandy Bridge MRC binaries
Change-Id: Ifd1a9f02d96bc7cf5d23706a09634c0353dfae61
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The microcode included for `model_6xx` was for a 660, that path has
changed.
Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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A liara specific VBIOS was released and merged to blobs. Now coreboot
need to point to the updated blob, so it can use liara specific VBIOS.
Liara Chromebook Stoney VBIOS BRT39865
BRT39865.001 12/05/18,01:13:54 CL#1716128 @ 15.49.0.18 ATOMBuild#436504
Major Changes included:
1. First Stoney VBIOS released to Liara update eDP power up sequence.
BUG=b:120534087
TEST=none
Change-Id: I3b060b1ccfb311584afd0fb66258eb7cc942408d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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New VBIOS code has been added to blobs/mainboard/google/kahlee. It has been
merged, so now coreboot needs to use latest blob.
BUG=b:112618193
TEST=none
Change-Id: If430ee06f03e0f20806bf8fd2b649814251ffcf5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I0032e86755750755e7ae6e2a53863e1600f96a5b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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* Include Cavium's CN81xx BL31.elf
* mainboard/google: Add folder kahlee for video binary
* Stoney Ridge: PSP bootloader update
* cpu/intel: remove microcode header files for model_306ax
Change-Id: Ie8f3b2e8db0692e95caee245733054e4e20f61ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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The two commits below are added to the BLOBs repository.
* fe7c6a3 pcengines/apu2: Disable ECC Exclusion range
* 3854ad2 cpu/amd/family_15h: Add latest AMD ucode file
The latest AMD microcode patches include Spectre mitigations.
Change-Id: I4729cc054fe8267549d7369cea4d26aa51861e1c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This adds the following changes to the blobs repository:
78a02a7 cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
In short: Bump Intel microcode updates. They include spectre/meltdown
mitigations.
Change-Id: I141f4446bc4e3bff5641bc39b70b299dc09ac8a7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/26270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This reverts commit 0ff9daac45d604fa4864394616e335e20af26c3e.
It points to a stale commit under review; i.e. not to a commit on
blob.git's master branch like it's supposed to.
Change-Id: I19cb8a32b3971c3104e381673ca08ae4d3979128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This moves the blobs submodule marker forward to include the following:
b45abbd cpu/intel: microcode: add license agreement
1d37962 cpu/intel: add microcode updates 20180312 for new CPU models
8b8bbce cpu/intel: apply microcode updates 20180312 to currently tracked models
in short: bump Intel's microcode updates to the latest version. This
includes Spectre/Meltdown mitigations.
Change-Id: I4ab74ae0bdcf2a109b0697ad233fbb812b5c4544
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/25505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.
BUG=b:70338633
TEST=build kahlee.
Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id a5efee5:
2018-01-04 16:24:19 -0700 - (Kahlee/Grunt: Move remaining stoneyridge blobs)
to commit id 19dea8d:
2018-02-01 08:51:06 -0700 - (soc/amd/Stoneyridge: Update PSP binaries to AGESA 1.3.0.9)
This brings in 2 new commits.
Change-Id: I7858ad8be13d9992949effb0216723d2480fa74d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23562
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were
moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob
to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it.
BUG=b:69613465
TEST=Build and run kahlee.
Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Update blobs pointer to bring in the AGESA.bin changes for
amd/00670F00/FP4 and amd/00670F00/FT4.
Change-Id: I739124090e41edaf76210cda6189b2c7545cdf58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add the binaryPI file for the FT4 package and add SMU firmware to
be consumed by fanless OPNs.
Change-Id: I1c9b5ded6b494fac1553cc2ec7756a7a47386ecf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Update the blobs submodule to bring in the binaries for 00670F00.
This also corrects some formatting in the various license.txt files.
Change-Id: I7a70d1168734d06ef6919d83dd73bc8f2bc4173c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17872
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins)
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The AGESA binary for PC Engines' APU2 board was just added to the blobs
directory. Update the submodule pointer to allow access.
Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16253
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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Change-Id: Ie57b0b7844f28671b8d6a8efe9231a47bfb8f805
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14745
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Update the 3rdparty/blobs submodule to bring in the latest
CarrizoPI binaries.
Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I208b012c6b612a94b3bbc8235d5a005028be8bcc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update to commit 832bc6f1 (Remove microcode stored in C-array format),
which is the latest commit in the BLOBs repository.
Building the Lenovo X60 currently fails as the microcode file cannot be
found.
CREATE build/mainboard/lenovo/x60/cbfs-file.wkWhPK.out (from src/mainboard/lenovo/x60/cmos.default)
make: *** No rule to make target '3rdparty/blobs/cpu/intel/model_69x/microcode.bin', needed by 'build/cpu_microcode_blob.bin'. Schluss.
Change-Id: I40ebceec299f46c19fd60861d872adcd91df3610
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I2071586e1f3b4464464928c11475f9283084dbcd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11693
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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b4ade40 via/nano: Move CPU microcode to 3rdparty/blobs
8921cc4 amd/model_fxx: Move CPU microcode to 3rdparty/blobs
1099605 amd/model_10xxx: Move CPU microcode to 3rdparty/blobs
5f5604e Convert microcode to binary
Change-Id: I276537281a01f8497ed87108e66574ec45265f3a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11129
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Makes the following changes available:
61d663e blobs: Fix assembler code to allow dropping -Wa,--divide
a6c34a6 AMD Steppe Eagle: add PlatformMemoryConfiguration.h
95b8050 AMD FT3b binary PI: Fix Windows 7 graphics driver hang
c7c816e AMD Kern: remove PspSecureOs_prod_CZ.sbin
Change-Id: Ie8ce8278f72c998b91717658a6fc1d0948c7c50a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Pick up the latest from blobs.
34b0926 AMD Merlin Falcon: remove build warnings
e581a5c AMD pi: replace LocateModule with agesawrapper_locate_module
c5ddfb6 AMD PI: remove unuseful code
Change-Id: I2b9d2b61cb00aa651b90dc76368d215077e27cad
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10603
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I2a9304a6b573a10e896f9ff77bfb09f20b21eb50
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10541
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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New marker includes:
3d5af98 microcode: Update Broadwell to MC0306D4_0000001F
349fd55 microcode: Update Baytrail to M0C30678_000082D
9077293 Add BLOBs to support AMD Embedded "Merlin Falcon" processor
Change-Id: I53f8f95079c6436ad316a11d432fcf92c03332b5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the 3rdparty/blobs marker to include the following:
a710941 amd/pi: Move AGESA cbfs access function to coreboot
63f1db5 AMD avalon: add PSP firmwares
Change-Id: Ie12b273ab9d22ab440b477919e70419b21cb833b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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There's now room for other repositories under 3rdparty.
Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the 3rdparty marker to blobs.git commit 892a697
Change-Id: I8a51f301e08e49970b4747f004e0752617de8005
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9625
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8613
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This pulls in the Intel microcode from blobs, and allows us to move
forward with relocating microcode updates in blobs.
Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8356
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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'blobs' now contains the update for the BaldEagle binaryPI.
Change-Id: I7ed423b17cee926205792223d6355277bedad552
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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'blobs' now contains the update for the Mullins binaryPI.
Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
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Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).
Apply that commit again:
'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.
Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.
Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support
binary AGESA release), which is the latest commit in the blobs
repository.
Change-Id: I3d643f7565700272c22b59ed764c3269801f4413
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7595
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Update the 3rdparty repo to the IPQ binary commit
This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c
Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: http://review.coreboot.org/7354
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
(cherry picked from commit cfa06c746023fbb79169260012539253811525aa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0
Reviewed-on: http://review.coreboot.org/7437
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Only one setting actually works (exact value depends on board). So
no need to show it.
Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7359
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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