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2020-05-13mainboard/lenovo/x230: Add ThinkPad x230s as a variantBill XIE
The code is based on autoport and that for X230. Major differences are: - Only one DDR3 slot - HM77 PCH - M.2 socket instead of mini pci-e - no docking - no tpm Tested: - CPU i5-3337U - Slotted DIMM 8GiB - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.9 within Debian GNU/Linux stable, loaded from Seabios. Untested: - Touch screen, which is said to work under ubuntu but not debian. Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-113rdparty/libgfxinit: Update submodule pointerMatt DeVillier
Update libgfxinit submodule pointer to pull in workaround for VT-d. Change-Id: I09f811bdb917365f4e97b7ab385781337d4c9cf7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41181 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-093rdparty/libgfxinit: Update submodule pointerNico Huber
Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-293rdparty/libgfxinit: Update submodule pointerNico Huber
This includes a huge set of refactorings to support Core Display Clock (CDClk) frequency switching based on the current mode requirements. The CDClk is configurable since Haswell and runtime switching is suppor- ted since Broadwell. Always using the lowest possible frequency setting should allow some power-savings. While, on the upper end, we can support higher resolution panels now, without having to change the static confi- guration. There have also been some smaller changes and fixes, including: o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't advertise a maximum link rate but only individual ones. o DP support for Ibex Peak. o Corrected limit for HDMI on G45 to 165MHz. o Reworked GMBUS reset handling and timeouts, should help with stalled GMBUS controllers when unimplemented ports were probed by accident. Tested on various boards from GM45 to KBL-R. Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35898 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-053rdparty/libgfxinit: Update submodule pointerNico Huber
Update libgfxinit: o Add support for ULX (CPU Y series) variants o Add support for Kaby/Coffee/Whiskey/Amber Lakes o Publish Read_EDID() procedure o Fix certain GMBUS error conditions o Fix DP training when clock recovery needed voltage-swing increase o Fix scaling on eDP for BDW+ Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-123rdparty/libgfxinit: Update for runtime CPU detectionNico Huber
Beside one tiny fix for framebuffer scaling, this contains a major refactoring of libgfxinit's configuration infrastructure. With this, we are finally able to detect CPUs at runtime and only have to confi- gure a CPU/GPU generation. Change-Id: Iccf4557453878536f527e4a1902439a1961ab701 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-213rdparty/libgfxinit: Update submodule pointerArthur Heymans
Updates to current master. This includes: - A fix for textmode scaling on G45 - Refactor things to rely less on inline proving - Increased width of modeline fields to 32 bits Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30311 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-083rdparty/libgfxinit: Update submodule pointerArthur Heymans
Update to current master. This includes: - G45 support - fixes scaling on eDP (needed for working textmode on eDP) - gfx_test drawing and moving cursors - Adding support for Tiling on <= Haswell - Allow changes to the framebuffer configurarion without resetting the pipe. Change-Id: I4ff3c17ec7308115de7bf2f2bb9276c2fad41253 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26823 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-233rdparty/libgfxinit: Update submodule pointerNico Huber
Update to current master. Beside a minor workaround for GCC 8 compatibility, this includes only refactorings and preparations for G4x support. Change-Id: I6b2aa6bd9d41b852dacd8e1dfe89d92c8a548121 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26420 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-133rdparty/libgfxinit: Update submodule pointerNico Huber
Update libgfxinit to current master. Changes include: * a fix to decode the size stolen memory correctly on pre-SandyBridge hardware, * a PCI id based generation check, obsoleting the old check based on PCH audio ids, * some minor improvements around rarely used DDI ports (D and E), and * added support for tiled and rotated framebuffers on Skylake+ hardware (less interesting for coreboot, I guess?). TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6 (Skylake) both with text and linear framebuffers and observed FILO's prompt showing up. Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25453 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12drivers/intel/gma: Power up legacy VGA block earlyNico Huber
This is required at least on Skylake to be able to configure text mode. 3rdparty/libgfxinit is also updated by the single commit: 42fb2d065d gma: Add procedure to power up legacy VGA block Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/21386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-083rdparty/libgfxinit: Update submodule pointerNico Huber
Update libgfxinit to the latest master. Changes: * Remove trailing whitespace in debug output. * Change some types to make it verify with SPARK Pro. * Add Broxton (Apollo Lake) support for eDP/DP/HDMI. * Add Linux user-space test tool `gfx_test`. * Add a README describing libgfxinit and the build process. TEST=Booted lenovo/t420 and verified that internal and external displays are working. Change-Id: I4d0e23b8a254234173461b831585eae58d3af58e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-04-083rdparty/libgfxinit: Update submodule pointerNico Huber
Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-153rdparty/libgfxinit: Update to latest masterNico Huber
Changes: o Verification that the framebuffer matches the display mode o Automatic upscaling if the framebuffer resolution is lower than the display mode's o VGA-plane support o HDMI pixel rate is limited to hardware constraints o Error tolerant handling of EDID header-pattern Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17775 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-11-29drivers/intel/gma: Hook up libgfxinitNico Huber
Add `libgfxinit` as another option for native graphics initialization. For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has to be called by the respective northbridge/soc code. A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and implement the Ada package `GMA.Mainboard` with a single function `ports` that returns a list of ports to be probed for displays. v2: Update 3rdparty/libgfxinit to its latest master commit to make things buildable within coreboot. v3: Another update to 3rdparty/libgfxinit. Including support to select the I2C port for VGA. Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-29Set up 3rdparty/libgfxinitNico Huber
`libgfxinit` is a SPARK library for graphics modesetting. It supports Intel integrated graphics only, strictly speaking, the Core i processor line. Change-Id: Idf4b0e5fbf37a5d974075b2e44d1fa16dc428da3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16949 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-053rdparty: Move to blobsPatrick Georgi
To move 3rdparty to 3rdparty/blobs (ie. below itself from git's broken perspective), we need to work around it - since some git implementations don't like the direct approach. Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-143rdparty: move checkout marker forwardStefan Reinauer
Move the 3rdparty marker to blobs.git commit 892a697 Change-Id: I8a51f301e08e49970b4747f004e0752617de8005 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9625 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-03-073rdparty: Update submodule to get Tegra 132 binariesMarc Jones
Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8613 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-273rdparty: Update to latest commit (for Intel microcode)Alexandru Gagniuc
This pulls in the Intel microcode from blobs, and allows us to move forward with relocating microcode updates in blobs. Change-Id: Iaa046cc20c7825aac168a6ed97c87be548634df3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8356 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-163rdparty: Update to latest commit in blobs repositoryDave Frodin
'blobs' now contains the update for the BaldEagle binaryPI. Change-Id: I7ed423b17cee926205792223d6355277bedad552 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-153rdparty: Update to latest commit in blobs repositoryDave Frodin
'blobs' now contains the update for the Mullins binaryPI. Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8230 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-283rdparty: Update to latest commit in blobs repositoryPaul Menzel
Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error occurs) unintentionally reverted commit 16472743 (3dparty: Update to latest commit in blobs repository). Apply that commit again: 'blobs' now contains updates which allow binary AGESA to build with Clang. Pull those in, in anticipation of re-enabling -Werror on Clang builds. Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7963 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-26nyan*: I2C: Implement bus clear when 'ARB_LOST' error occursTom Warren
This is a fix for the 'Lost arb' we're seeing on Nyan* during reboot stress testing. It occurs when we are slamming the default PMIC registers with pmic_write_reg(). Currently, I've only captured this a few times, and the bus clear seemed to work, as the PMIC writes continued (where they'd hang the system before bus clear) for a couple of regs, then it hangs hard, no messages, no 2nd lost arb, etc. So I've added code to the PMIC write function that will reset the SoC if any I2C error occurs. That seems to recover OK, i.e. on the next reboot the PMIC writes all go thru, boot is OK, kernel loads, etc. BUG=chrome-os-partner:28323 BRANCH=nyan TEST=Tested on nyan. Built for nyan and nyan_big. Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197732 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc Reviewed-on: http://review.coreboot.org/7897 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-223dparty: Update to latest commit in blobs repositoryAlexandru Gagniuc
'blobs' now contains updates which allow binary AGESA to build with clang. Pull those in, in anticipation of re-enabling -Werror on clang builds. Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-013rdparty: Update to latest commit in blobs repositoryPaul Menzel
Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support binary AGESA release), which is the latest commit in the blobs repository. Change-Id: I3d643f7565700272c22b59ed764c3269801f4413 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7595 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-11blobs: Update to IPQ blob commitMarc Jones
Update the 3rdparty repo to the IPQ binary commit This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: http://review.coreboot.org/7354 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> (cherry picked from commit cfa06c746023fbb79169260012539253811525aa) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0 Reviewed-on: http://review.coreboot.org/7437 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-09Kconfig: Hide DYNAMIC_CBMEM.Vladimir Serbinenko
Only one setting actually works (exact value depends on board). So no need to show it. Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7359 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-08blobs: Update to IPQ blob commitMarc Jones
Update the 3rdparty repo to the IPQ binary commit Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7354 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-01AMD Steppe Eagle: Update reference to BLOBs repo (3rdparty)Bruce Griffith
The BLOBs repo has been updated with AMD PI header files, peripheral BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for Steppe Eagle, the Steppe Eagle video BIOS, and platform security processor firmware. Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-01acpigen: Add acpigen_emit_eisaid.Vladimir Serbinenko
Change-Id: Ib92142a133445018cd152dabe299792ba5f36548 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5240 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-113rdparty: update to current HEADPatrick Georgi
It includes a sandybridge fix. Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-18AMD Yangtze: Update 3rdparty hash for new blobsBruce Griffith
Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Update 3rdparty hash for latest ARM BL1 binariesStefan Reinauer
Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3740 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-06-28Update 3rdparty mark to latest repositoryStefan Reinauer
For new systemagent v6 binaries. Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3567 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-15Update 3rdparty mark to latest repositoryStefan Reinauer
For google/stout binaries Apparently the actual marker got lost in the rebase / change of the commit message. Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-13Eagleheights DSDT: Grant OS control through OSCMike Loptien
Change the OSC method to actually grant control of PCIe capabilities to the OS instead of granting no control. I believe the logic was backwards in the original commit. Bits should be set when granting control and cleared when not granting control. By setting the return value to 0x00, we effectively tell the OS that it cannot control any PCIe capability. See section 6.2.9 of the ACPI spec version 3.0 for more information. This edit is a duplication of the OSC method that is in the src/southbridge/intel/bd82x6x/pch.asl file. Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2714 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13Update 3rdparty mark to latest repositoryStefan Reinauer
For google/stout binaries Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2635 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-22Update 3rdparty mark to latest repositoryStefan Reinauer
Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2480 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-02-11Update 3rdparty mark to latest repositoryStefan Reinauer
Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-05Update 3rdparty mark to latest repositoryStefan Reinauer
Change-Id: I59fca4427345c7e677138b944613a1554d5a8331 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2110 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-12Update 3rdparty to it's HEADStefan Reinauer
Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2025 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-17Use new system agent binariesStefan Reinauer
Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1879 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Updated submodule referenceStefan Reinauer
Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a Reviewed-on: http://review.coreboot.org/1816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-19Finally update 3rdpartyPatrick Georgi
Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1242 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-01Add 3rdparty as submodulePatrick Georgi
The build system will make sure only to fetch this if desired by the user. Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 16:33:36 +0000