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Updating from commit id 9d4053d:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 48195e5:
2020-11-24 10:23:45 +0000 - (Makefile: Test for warning flags before using them)
This brings in 3 new commits.
Change-Id: I64f27f346df264cb6eeeb4e3203fcca7d35f7e83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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Updating from commit id 4c523ed1:
vboot2: Add support for modexp acceleration
to commit id 9d4053df:
Revert "Reland: Clean up implicit fall through."
This brings in 32 new commmits. Among the changes are restored support
for older GCC/clang versions that do not support
__attribute__((fallthrough)).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This now tracks a recently created upstream repository located at
https://github.com/amd/firmware_binaries
BUG=b:166107781
Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The 3 commits commits from the blob repository this patch pulls in
remove executable flags from files in the repo that shouldn't have those
flags set:
* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit
* Remove execute permission from all binaries
* Remove execute permission from plaintext files
Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Updating from commit id 4bb06cc1:
COIL: Change denylist to blocklist
to commit id 4c523ed1:
vboot2: Add support for modexp acceleration
This brings in 10 new commmits.
Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This pulls in the following changes:
* soc/intel/baytrail/microcode.bin: Remove outdated microcode
* mainboard/amd/mandolin: add Cereme APCB
Change-Id: If6dd7881b346782635dec07710fe5c4449254e3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch incorporates the STM build as a part of the coreboot
build. A separate patch lists and documents the options that
the developer can use. In most cases the default options will
suffice.
Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796
Signed-off-by: Eugene D Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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Updating from commit id 3bd9078:
2020-08-12 17:03:38 -0600 - (picasso: Update PSP to 0.8.6.7B)
to commit id e393a88:
2020-09-16 14:32:50 +0000 - (Update SMU firmware for Picasso, Pollock and Dali)
This brings in 1 new commits.
Change-Id: I1e317cf6ef4803577e9b353fb3313d001db228d7
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45455
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id fefcaa65:
vboot: adjust VB2_SECDATA_KERNEL_FLAGS in non-recovery path
to commit id 4bb06cc1:
COIL: Change denylist to blocklist
This brings in 20 new commmits.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Project: https://github.com/9elements/converged-security-suite
License: BSD-3
Tooling for Intel platform security features
Change-Id: I7421b30eb38e64cf6b77b7e1c485c5700728997b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45057
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
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Updating from commit id ace23683b:
2019-09-27 Merge changes from topic "ld/stm32-authentication" into
integration
to commit id a4c979ade:
2020-08-26 Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
This brings in 1825 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id26301dae421eec61c10a2d18842053f3228c557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 3932b1c:
2020-08-19 02:09:04 +0000 - inclusive: change usage of
blacklist/whitelist
to commit id fefcaa6:
2020-08-24 04:32:03 +0000 - vboot: adjust VB2_SECDATA_KERNEL_FLAGS in
non-recovery path
This brings in 2 new commits.
Change-Id: Ia3ff764537b91f76ba6fa3ba2646638964800510
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This also includes https://chromium-review.googlesource.com/2318026
which fixes an issue with duplicate symbols.
Change-Id: Icf450616b3bcd8b7c01261c913cd172625dbd6ba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update PSP to 0.8.6.7B.
BUG=b:163857965
TEST=none
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I634dadccc51b36f9ac25c3238a794564ce580d5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia250765e2cb81d6a39ad00ebbab20e7b87fa42d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43758
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:162057232
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ifd4ac0655f7ada5ec10a266fdb2b930861959215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44040
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Building depthcharge master currently fails as depthcharge commit 74ca8ae5
(depthcharge: Hide dev mode timeout description) changed the function signature
according to vboot commit 59fd331b (vboot/ui: pass timer_disabled to
vb2ex_display_ui()), which is not yet present in the vboot checkout:
$ make
[…]
CC drivers/ec/vboot_auxfw.depthcharge.o
src/drivers/ec/vboot_auxfw.c: In function 'display_firmware_sync_screen':
src/drivers/ec/vboot_auxfw.c:117:5: error: too many arguments to function 'vb2ex_display_ui'
vb2ex_display_ui(VB2_SCREEN_FIRMWARE_SYNC,
^~~~~~~~~~~~~~~~
In file included from /dev/shm/coreboot-1/3rdparty/vboot/firmware/include/vb2_api.h:18,
from src/drivers/ec/vboot_auxfw.c:17:
/dev/shm/coreboot-1/3rdparty/vboot/firmware/include/../2lib/include/2api.h:1262:13: note: declared here
vb2_error_t vb2ex_display_ui(enum vb2_screen screen,
^~~~~~~~~~~~~~~~
So update the submodule pointer from commit 68de90c7 (Allow building for
non-CrOS environments) to commit ed23c084 (Reset EC when transitioning to dev
mode).
This brings in 7 new commits.
Change-Id: Icd5408fb824fc5da470774b7f493b916dff17832
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
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This brings in 4 new commits:
* c0db994 common/Makefile.inc: Factor out generation TLAs
* 3f86b0b Move `PSR_Off` out of `Power_And_Clocks_Haswell`
* 450c24c haswell: Make VGA on FDI work
* 3318bf2 Drop generation suffix from `Power_And_Clocks`
Change-Id: I023b0c2bb403b3a9c9fe575a78cd2cf2f20b112a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This brings in 5 new commits:
* 69e9086 mutime: Make Sinfo an imported constant
* 9f87a10 time: Add T_First constant
* 4e22910 Makefile: Adapt $(space) definition
* d822df5 Makefile: Delay expansion of `$(ADAFLAGS)`
* a3edc6e Makefile: Add `-gnatw_R` to suppress spurious warning
Change-Id: I907e66fcf85da256a112a7069a3c551a6d8caaf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id c531000f:
2020-05-18 20:55:55 +0000 - (vboot: Add recovery reason code for CSE Lite SKU errors)
to commit id 68de90c7:
2020-07-02 11:31:05 +0000 - (Allow building for non-CrOS environments)
This brings in 59 new commits.
Change-Id: I7f3c30511ff4acc60e3581bdab89d685dc7beaa5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43008
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I752804919227c1522374b93e08abee13396b2679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Changes in 3rdparty/blobs:
* Update of the OCP Tiogapass Flash descriptor binary
* Move binary policy as README.md
* Markdownify README.md
* Add APCB binary for AMD Mandolin
Change-Id: I0c45969626f30dca42bba1f137e85ec0999fc671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This pulls in a newer version of the PSP-related blobs.
Change-Id: I6ff39260e9697512f78eb68435bd17ea83af35d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:157140753
TEST=Built zork/trembyle and boot to OS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I30a27a149ee7f368f45fdf5d4a081127f15e7629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Cmocka unit testing framework is used for writing and building coreboot
unit tests. This repo will be checked-in only when building some test
targets.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I3cdfd32f5bba795d5834ebeae1afff0f7006a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change updates vboot submodule from commit hash 3aab301:
vboot: Convert reboot-related errors to vboot2-style
to commit hash c531000:
vboot: Add recovery reason code for CSE Lite SKU errors
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ifbf5a09e6602c3f6833e6e8fbbd3cee3f60f1b47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I468f0d3ab018ee0044e8de7df829c64940c7df2b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Update libgfxinit submodule pointer to pull in handling for
presence straps bypass and some minor cleanup.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Id4a903383f32f352aa3595bd72bc5f6f0777171c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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6b95507ec5b087658178a325bdc68570bc48bb20 has mistakenly reverted
the submodule pointer of 3rdparty/libgfxinit to cdbfce27, canceling
c844d14ca5081b2cb2f1036bdf0c2112405342d1.
This commit sets it back, recovering c844d14c.
Change-Id: Ib594e40a39ea83dd2238becb287f2516e7c54046
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41400
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie886815ed354762ea52fd6a76169cf25576f8852
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The code is based on autoport and that for X230. Major differences are:
- Only one DDR3 slot
- HM77 PCH
- M.2 socket instead of mini pci-e
- no docking
- no tpm
Tested:
- CPU i5-3337U
- Slotted DIMM 8GiB
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- Linux 4.9 within Debian GNU/Linux stable, loaded from
Seabios.
Untested:
- Touch screen, which is said to work under ubuntu but not debian.
Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Update libgfxinit submodule pointer to pull in workaround for VT-d.
Change-Id: I09f811bdb917365f4e97b7ab385781337d4c9cf7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41181
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 55154620:
vboot: Add screens for recovery using disk
to commit id 3aab3014:
vboot: Convert reboot-related errors to vboot2-style
This brings in 3 new commits.
Change-Id: I75be535e0b0f8080366b98e5ae2007452ad51738
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40845
Reviewed-by: Joel Kitching <kitching@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update submodule pointer to 20191115 release to include the microcode
update for CML-U62, and others.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I4765a70be0b1182acd340a3c31a5d71fd0ab500f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Updating from commit id 46ff62c3:
vboot: stop reading from ACPI for wpsw_boot
to commit id 55154620:
vboot: Add screens for recovery using disk
This brings in 37 new commits.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ie184cbe6cc18cea540966d5801472ae821ea3e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40503
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the pointer for vboot_reference so it can be used to compile
depthcharge payload on the master branch.
Change-Id: I5fc6e05896d7221a1e48ca86c6b15081488302b5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 8b9732f5:
2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was
meant to be)
to commit id 5059062d:
2020-03-05 02:40:39 (EFS: Implement EFS2 and NO_BOOT mode)
This brings in 19 new commits.
Change-Id: Ic33500921e2c1a6109c24ad36713b41ab6e43de9
Signed-off-by: dnojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39324
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating from commit id 0e97e25e:
2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was meant to be)
to commit id 8b9732f5:
2020-02-18 05:55:01 +0000 - (vboot: do not call vb2_commit_data at end of VBSLK)
This brings in 36 new commits.
Change-Id: Icb0ab2c82c3264185171a32357944949afd2edce
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I5f053c1270bab71aeab3bb785c60417419736b44
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Updating from commit id 6ef33b99:
2019-11-22 Hung-Te Lin futility: updater: refactor: unify
getting temp files for firmware images
to commit id 0e97e25e:
2020-01-23 Julius Werner 2lib: Fix struct vb2_hash the way it was
meant to be
Change-Id: I539aba2f283804f67ff3ff4f98324b3d10b2bb54
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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Updating from commit id 2843aa62:
2019-12-12 Julius Werner 2lib: Move firmware body size reporting to
separate function
to commit id f5367d59:
2020-01-20 Joel Kitching vboot: translate recovery reason info from
vboot 2->1
This brings in 27 new commits.
Change-Id: I7d33337881fa2d36d6e562b0a390b56227cfad55
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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Kconfig default paths already point into `3rdparty/amd_blobs/`.
Change-Id: Ibb6f12183c48c7c07f76e794b4971c8b75116333
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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We had to role the `fsp` submodule back for a minute due to a regression
with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into
the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and
heap usage partitioned for FSP using coreboot's stack (config FSP_USES_
CB_STACK), it works again.
To make this even messier: We already selected this Kconfig option for
Whiskey Lake, which is supposed to use the very same FSP binary. So with
either submodule pointer, something was always broken :-/
Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
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CB:36845 simplified how coreboot finds the RW CBFS after vboot has and
eliminated a layer of caching. Unfortunately, we missed the fact that
the former cached value didn't exactly match the FMAP section... it was
in fact truncated to the data actually used by vboot. That patch
unintentionally broke this truncation which leads to performance
regressions on certain CBFS accesses.
This patch makes use of a new API function added to vboot (CL:1965920)
which we can use to retrieve the real firmware body length as before.
(Also stop making all the vb2_context pointers const. vboot generally
never marks context pointers as const in its API functions, even when
the function doesn't modify the context. Therefore constifying it inside
coreboot just makes things weird because it prevents you from calling
random API functions for no reason. If we really want const context
pointers, that's a refactoring that would have to start inside vboot
first.)
This patch brings in upstream vboot commit 4b0408d2:
2019-12-12 Julius Werner 2lib: Move firmware body size reporting to
separate function
Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Updating from commit id 695c56dc:
2019-12-04 Julius Werner Makefile: Make loop unrolling fully
controllable by the caller
to commit id b10e5e32:
2019-12-09 Yu-Ping Wu vboot: Make 2nvstorage.h private to
vboot_reference
This brings in 19 new commits.
Change-Id: I9cdccd25422aee26620d48d31f83bcf32a7b4809
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37717
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With CB:37564 (3rdparts/fsp: Update fsp submodule) a regression
has been introduced to CFL platforms, such that the FSP-M fails/is
broken. This commit sets the commit to checkout in the submodule
FSP back to a working version.
Change-Id: I8eac551211559962fc60e7edd46ff118d7bde830
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37669
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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