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2018-01-10util/lint: Check license headers of git hooksAlex Thiessen
Now that all the files under util/gitconfig have their license headers, enable lint-000-license-headers to check the directory too. Change-Id: I242256f72ac70553535509f83166c6d1ddb16fdc Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-10util/gitconfig: Add missing license headersAlex Thiessen
License header for the `gitconfig.sh` was copied from the Makefile it was extracted from in commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script). License header for the pre-commit hook names Patrick Georgi as the copyright holder as he is the original author. Change-Id: Ie051e5e6ae7571050ece383e6be8236ed7d1ddd9 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-10mainboard/google/kahlee: Update SPD MakefileMartin Roth
The .spd.hex text is added to the name by the build process. This was causing a failure because we were trying to add the files: 'file.spd.hex.spd.hex' to the build. Remove the additional .spd.hex text. BUG=b:71535311 TEST=Build Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-01-09mb/google/fizz: Turn off SATA SALPKevin Chiu
turn off SATA SALP to prevent 0x5A/0x5B error on Sandisk SSD in below conditions: 1. reboot stress 2. FAFT BIOS qualification BUG=b:70146894,b:69984821,b:70590720 BRANCH=master TEST=pass firmware_ConsecutiveBoot 2500 loops FAFT BIOS test pass Change-Id: I5d57dd8ef256d5f0a1027ab77f63da62c6c9ce74 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-09mainboard/google/zoombini/variants/meowth: add new boardNick Vaccaro
Add Meowth board, which derives from Zoombini, a CNL reference board. BUG=b:69011806 BRANCH=master TEST=Compiles successfully using "./util/abuild/abuild -p none -t google/zoombini -x -a" and boots Meowth. CQ-DEPEND=CL:22908 Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-09mainboard/google/zoombini: Provide memory configuration variant APINick Vaccaro
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-09soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik
This patch ensures all CannonLake CPUIDs are part of mp_init.h hence remove duplicate macro definitions from SoC code. TEST=Build and boot CannonLake RVP Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-09mb/google/poppy: Add internal pull-up on pen eject signalFurquan Shaikh
Since the current hardware revision does not have external pull on the pen eject signal, this change adds internal pull-up on it. Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-08soc/amd/stoneyridge/i2c: fix formatting and global symbolAaron Durbin
The i2c_bus_address array doesn't need to be a global symbol. Also, the array initializer had some weird indention and there was an extra new line. For consistency the first entry is multiplied by 0 so the formatting is similar. BUG=b:69416132 Change-Id: I74f6dca3a22a245759536f792ce04ac61735b6d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-01-08google/gru: switch to spi2 for all scarlet based boardsEge Mihmanli
Rainier, a scarlet derived board, was configured to use spi0 for tpm driver by default. This patch switches it to spi2 to reflect recent changes in scarlet-derived boards. Change-Id: Ib67109786512c068bb957890f456bccff7addc86 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-08soc/intel/cannonlake: Initialize DDI-A lane in Normal modeAbhay Kumar
Enable DDI-A (eDP) when pre-OS graphics is not Loaded or in normal mode. This will make sure that kernel will detect eDP. TEST=Edp should come up in normal mode. Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/22799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-08soc/amd/stoneyridge: Define CONSOLE_UART_BASE_ADDRESSArthur Heymans
The build system for the SeaBIOS payload needs this when DRIVERS_UART_8250MEM is set. Set it to the first uart controller, which the coreboot code also seems to do. Fixes: https://ticket.coreboot.org/issues/150 Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-07superio/ite/it8623e: add support for SIO chip ITE IT8623EGergely Kiss
This change adds basic support for the SuperIO chip ITE IT8623E. Due to the lack of a datasheet, defaults are shown as "not available (NA)" in superiotool's register dump. LDNs defined in it8623e.h are definitely correct and working as expected. Change-Id: I05832c4db7ab59541337f11200640316376e792e Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07soc/amd/common: Only load post-memory AGESA into RAM when split enabledDaniel Kurtz
CONFIG_AGESA_SPLIT_MEMORY_FILES controls whether AGESA is split into pre- and post-memory binaries when it is built. Building AGESA this way is required when doing the new "load post-memory AGESA binary into ram" feature. Thus, condition this new path on the CONFIG option being enabled. BUG=b:71641792 TEST=build and boot kahlee with CONFIG_AGESA_SPLIT_MEMORY_FILES disabled Change-Id: Ibec9db67437c57092e0f7acf0e3185865dc02688 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23141 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-07autoport: Add Intel PCIe Root Port and BridgesJean Lucas
- 0x0151: Xeon E3-1200 PCIe Root Port - 0x1e25: 7/C216 Series Chipset Family DMI to PCI Bridge - 0x2448: 82801 Mobile PCI Bridge - 0x244e: 82801 Desktop PCI Bridge Change-Id: I4111b73adc0f08d643c940cd43ab7fd4c0af7668 Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/22794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07soc/intel/cannonlake: provide LPDDR4 memory initNick Vaccaro
Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-073rdparty/blobs/soc/amd/stoneyridge: Use new location of stoneyridge blobRichard Spiegel
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it. BUG=b:69613465 TEST=Build and run kahlee. Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-07mainboard/ms7721: Fix temperature sensor configurationRenze Nicolai
This patch allows temperature sensors 1 and 2 to function by setting their type to be thermistor instead of BJT. Change-Id: I6491171eacc0c9848ba86ba7a62ec440226aae36 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07mainboard/nf81-t56n-lf: Add temperature sensor configurationRenze Nicolai
This patch adds the temperature sensor type device tree setting, configured to be the default value as stated in the Fintek f71869ad datasheet on page 60. bit 7-4: reserved (0) bit 3: T3_MODE 1 (default) = BJT, 0 = thermistor bit 2: T2_MODE 1 (default) = BJT, 0 = thermistor bit 1: T1_MODE 1 (default) = BJT, 0 = thermistor bit 0: reserved (0) This results in a default value of 0x0E This change is needed to make sure behaviour does not change after applying change 22935 which adds the temperature sensor type devicetree configuration option Change-Id: I42980988267621def6576f771f1d8a853500e867 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07superio/f71869ad: Add temperature sensor typeRenze Nicolai
This patch makes it possible to set the "Temperature Sensor Type Register" at index 6Bh from the devicetree, allowing the use of thermistors instead of BJT type sensors. Register documentation (from page 60 of the F71869 datasheet): 6.6.25 Temperature Sensor Type Register - Index 6Bh Bit 7-4: reserved Bit 3: T3_MODE (0: thermistor, 1: BJT [default]) Bit 2: T2_MODE (0: thermistor, 1: BJT [default]) Bit 1: T1_MODE (0: thermistor, 1: BJT [default]) Bit 0: reserved Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07intel/dcp847ske: Add superio ACPI declarationsTobias Diedrich
Tested on Linux 4.13.14: SuperIO resources show up as reserved in /proc/ioports and friends. Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07nuvoton/nct6776: Add ACPI declarationsTobias Diedrich
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Tested on Intel NUC DCP847SKE, Linux 4.13.14. Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-06superio/ite: add missing pnp_conf_mode fields in ops structFelix Held
This fixes the bug that the LDNs on the affected SIO chips didn't get configured, since the config mode wasn't entered. Change-Id: Ic468847571e164e4e1280428f08fc067b724464e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-05mainboard/google/zoombini: Add SoC acpi files to dsdt.aslNick Vaccaro
BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I417a1c606e4968120414af57aa3b17d5c3b3cad0 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-05mainboard/google/zoombini: Fix some devicetree pci settingsNick Vaccaro
- Enable I2C #2, #3, and #5 - Enable UART #2 - Enable GSPI #0 and #1 - Disable SATA - Set pci 1f.0 to chromeec BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-05mainboard/google/zoombini: add mainboard_opsNick Vaccaro
Add mainboard.c to ramstage. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: Ic7275b07f28a99a91b978d2e8c4118c6858705bc Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-05vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v77_12Srinidhi N Kaushik
Update FSP header files to match FSP v77_12 Following fields have been added in FSP-S UPD: - SkipPunitInit (Skip P-unit Initialization) - HgSubSystemId (Sub system Vendor ID VGA) Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22820 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-05sb/intel/i82801ix: Don't select HAVE_INTEL_FIRMWARE on Q35-QEMUArthur Heymans
The Qemu q35 target doesn't support or needs Intel Firmware blobs so it doesn't make sense to select that option on this hardware. The result of this change will be that when changing the ROM chip size, CBFS_SIZE will automatically fill the whole flash which is desirable in this case. Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23090 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-05mainboard/google/kahlee: Update Grunt devicetree.Justin TerAvest
Grunt's devicetree dropped some entries when it was split from the kahlee variant. This commit restores: spd_addr_lookup - memory information for AGESA dram_clear_on_reset - keeps DRAM contents on reset uma_mode - needed for vbios uma_size - needed for vbios Change-Id: I1d8cdc97594867f1d706318370055087976a5104 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao
PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-05soc/amd/common: load post-memory AGESA as rmoduleAaron Durbin
Now that the AGESA binary is split into two sections load the post-memory AGESA binary into ram. It needs to be an rmdoule so that it can be relocated into ram. agesawrapper_amdinitenv() entry CBFS: 'VBOOT' located CBFS at [10000:cfd40) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset 875c0 size 11c5e Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes) Loading module at c7580000 with entry c7580000. filesize: 0x2bafc memsize: 0x2bb0d Processing 1112 relocs. Offset value of 0xc7780000 AGESA call 00020001 using c75818fe AGESA call 00020003 using c75818fe Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS BUG=b:68141063,b:70714803 TEST=Booted kahlee. Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: Allow AGESA file split for pre- and post-memoryJustin TerAvest
By splitting the binary files for platform initialization, the post-memory code can be modified to stop executing in place (--xip). This change creates two separate sections in CBFS for AGESA and loads the appropriate file at the correct stage. BUG=b:68141063 TEST=Booted kahlee with split agesa enabled. Change-Id: I2fa423df164037bc3738476fd2a34522df279e34 Signed-off-by: Justin TerAvest <teravest@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-04util/gitconfig: Do not wait for user inputAlex Thiessen
When running `make gitconfig` on a freshly cloned repository, the script will wait for user input without a prompt in a call to `sed`, caused by a spurious newline introduced in commit 9ab8ae6a (util/gitconfig: Make gitconfig a bash script). Change-Id: I2aa722c052d24dcffa9688df09bcf8dc767bd0b6 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-04util/gitconfig: Support dash in pre-commit hookAlex Thiessen
On debian systems, /bin/sh is `dash` which has built-in `echo` always interpreting escape sequences such as '\n'. The pre-commit hook uses the built-in for piping diff to checkpatch, interpreting the diff's escape sequences in the process and leading to false negatives and preventing commits despite conformance. Use `printf` instead of `echo` when handling diff content. The bug was introduced in commit ef869305 (util/gitconfig: update pre-commit script). Change-Id: I37edfe7b32721cb63d99299563cb11f26082c9a9 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-03soc/amd/stoneyridge: Add I2C supportChris Ching
BUG=b:69416132 BRANCH=none TEST=make Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02soc/amd/common/block/pi: Format files to standardsRichard Spiegel
Files agesawrapper.c and heapmanager.c have several non-conformity with coreboot standards, including lines longer than 80 characters, use of "} else {" after a return and wrong comment block formatting. Fix all such issues, so that it passes commit tests. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, just file formatting). Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02mb/google/poppy/variants/nami: Add empty_ddr4.spd.hex for DDR4Kane Chen
The spd size of DDR4 is 512, but the size empty.spd.hex is 256. With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data loads spd data incorrectly due to the offset is wrong. Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-02google/fizz: Enable SataPwrOptEnable FSP UPDKane Chen
This change is to enable SataPwrOptEnable. With this change, we no longer see SError message in kernel during suspend_stress_test. BUG=b:70491485 Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-02soc/intel/skylake: Add device setting for sata power optimizationKane Chen
This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose BUG=b:70491485 Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-25mb/hp: Add CMOS support for all HP Elitebook modelsIru Cai
The cmos.layout files are copied from lenovo/x230 with EC options removed. It's tested on 8470p and the power_on_after_fail option works. Change-Id: I0a50a25798fd31b7acccf9872c50dac2718ce895 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-25ec/hp/kbc1126: change the default offset of the blobsIru Cai
Using Kconfig options USE_OPTION_TABLE, BOOTBLOCK_NORMAL makes the bootblock to 4200 bytes, so the offsets of these blobs need to be put at a lower address. Change-Id: I8754e43ff318a03447633f7a9a8326d315328607 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-24drivers/mrc_cache: Make CACHE_MRC_SETTINGS not selectableArthur Heymans
Don't allow the user to select this manually, since it doesn't build on platforms that don't use it. Don't set the bool value so that it doesn't show as not selected in the .config file of platforms that don't use this. Change-Id: Icf026a297204868d485be270ccee7e0bec0ac73b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-23soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
BUG=b:70628116 Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22956 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-23soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides a new Kconfig option that can be selected by SoCs using these new bit definitions of SPI_CS_CONTROL. Common code takes care of setting the right value for polarity and state field depending upon the version selected by SoC. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-23soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in ↵Subrata Banik
weak function This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22mb/intel/dcp847ske: remove reference to non-existent fileAaron Durbin
In commit 7a95204 (intel/dcp847ske: Add Intel NUC DCP847SKE) the default_irq_route.asl file was removed, but this mainboard was missed. Follow suit with the original intent of the commit and fix the build breakage. Change-Id: I909dad7cfc0fab37e29187b2358f7f056216a403 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22975 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22purism/librem_skl: Improve boot time by enabling SPD Word ReadYouness Alaoui
This speeds up the SPD read ('calling FspMemoryInit' phase) from 218ms to 134ms consistently. Tested on both the Librem 13 v2 and Librem 15 v3. Change-Id: I44fbe96c256972bd074537159771d61fe7adf082 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-22soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()Richard Spiegel
Issue first reported at commit 1587dc8a2b, the call of functions setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev() to soc_init(). The function setup_uma_memory() no longer exists, its functionality transfered to agesawrapper_amdinitpost. Move setup_bsp_ramtop() as required. BUG=b:62240756 TEST=Build and boot kahlee. Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-22soc/intel: Treat time-out as failure in HECILijian Zhao
If HECI gets times out when waiting for read slots, there's no need to read back reply message to decide if the HECI recieve successed or not. Otherwise, system will stuck after global reset required. BUG=b:707290799 TEST=Boot up meowth board without battery, and confirm hard reset got trigged after heci time out. Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 04:26:28 +0000