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2015-08-27cbfstool: update warning on cbfstool extractPatrick Georgi
We have tons of file types now that can be safely extracted. It's pretty much only stages and payloads that aren't. Change-Id: Ibf58a2c721f863d654537850c6f93d68a8a5bbeb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27cbfstool: update help textPatrick Georgi
cbfstool create doesn't accept alignment configuration anymore. Change-Id: Idbf7662c605aa78e3d3413a21bfcbc1387f28701 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11358 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27cbfstool: don't pass header_size as separate argument (part 2)Patrick Georgi
It's already present inside struct cbfs_file Change-Id: Ic9682e93c3d208e2ed458940e4a9f9f5a64b6e98 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11333 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27cbfstool: don't pass header_size as separate argumentPatrick Georgi
It's already present inside struct cbfs_file Change-Id: Ib10663c6601aa02e07b868e440f05da02af9c2d9 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11332 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27cbfstool: use struct cbfs_file * instead of void *Patrick Georgi
My concern was that compilers may something stupid under the assumption of a fixed struct size, but filename is already variable, so things are okay. Change-Id: I5348faf68f0a7993294e9de4c0b6c737278b28af Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27cbfstool: passing a header is now mandatory for convertersPatrick Georgi
Change-Id: Iea5377af735b06bcaefb999547a8896b1c70763a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11330 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27cbfstool: cbfs_add_entry() doesn't need to know filename or typePatrick Georgi
They're passed as part of the header now. Change-Id: I7cd6296adac1fa72e0708b89c7009552e272f656 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11327 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27google/storm/Kconfig: remove select CONSOLE_CBMEM_DUMP_TO_UARTMartin Roth
This seems like more of a debug option, than something that should be forced to be enabled by the platform. Since it's causing a Kconfig warning, I'm just removing it. The alternative to removing it would be to add dependencies on CONSOLE_CBMEM && !CONSOLE_SERIAL Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11343 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-27skylake: only generate ACPI cpu entries onceAaron Durbin
The acpi_fill_ssdt_generator function pointer is evaluated for each device. As there are multiple cpus in the system the acpi_fill_ssdt_generator was being called more than once creating duplicate ACPI entries because there was more than 1 cpu device. Fix this by only generating them once by removing the acpi_fill_ssdt_generator for the cpu devices, but add the generator to the cpu cluster device. BUG=chrome-os-partner:44084 BRANCH=None TEST=Built and booted on glados. Noted ACPI entries only generated once. Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294240 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11285 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27skylake: FAB3 Adding Support for various SPD.pchandri
This pach enables memory configuration based on PCH_MEM_CFG and EC_BRD_ID. BRANCH=None BUG=chrome-os-partner:44087 CQ-DEPEND=CL:293832 TEST=Build and Boot FAB3 (Kunimitsu) Original-Change-Id: I7999e609c4b0b3c89a9689ee6bb6b98c88703809 Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293787 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I52a1af1683b74e5cad71b9e4861942a23869f255 Signed-off-by: pchandri <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/11284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27skylake: make PAD_CFG_GPI default to GPIO ownershipAaron Durbin
The prior implementation of PAD_CFG_GPI kept the pad ownership as ACPI. The gpio driver in the kernel then wouldn't allow one to export those GPIOs through sysfs in /sys/class/gpio. Fix this by setting the ownership to GPIO. BUG=chrome-os-partner:44147 BRANCH=None TEST=Built and boot glados. PCH_WP gpio is properly exported by crossystem. Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294081 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11283 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27glados: Abstract board GPIO configuration in gpio.hDuncan Laurie
Move all the various places that look at board specific GPIOs into the mainboard gpio.h so it can be easily ported to new boards. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados p2 Original-Change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I93c4dc1795c1107a3d96e686f03df3199f30de8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11282 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27glados: Implement Chrome OS specific handlersDuncan Laurie
Implement the required Chrome OS specific handlers to read the recovery mode, clear the recovery mode, read the lid switch state, and read the write protect state using the appropriate methods. Also update the Chrome OS ACPI device to use the GPIO definitions that are exposed now by the SOC. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados and successfully enter recovery mode Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293515 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27chromeec: Add helper function to read EC switch stateDuncan Laurie
Add a helper function to read the EC switch state on LPC based ECs instead of having each board need to understand and use the specific EC LPC IO method that is required. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293514 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11280 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Fix SPD part number for Hynix H9CCNNN8JTBLARDuncan Laurie
The part number was the same as the H9CCNNNBLTLAR which means it is not possible to distinguish the two based on part number alone. This breaks mosys and thus the factory tests. BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 SKU3 and verify memory reported by mosys Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Add touchscreen device in ACPIDuncan Laurie
Add the ELAN touchscreen device in ACPI to bind it to the I2C device at bus I2C0, address 0x10, interrupt 31 (GPP_E7). BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 and see touchscreen initialized by kernel Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293512 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27glados: Clean up mainboard ACPI devicesDuncan Laurie
Clean up the device code for the glados mainboard, using the defined values for interrupts by the SOC and moving the various codec i2c addresses to the top of the file. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293511 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27kunimitsu: Enable SMBus device in devicetreeNaveen Krishna Chatradhi
this patch enables SMBus in device tree for kunimitsu board. BRANCH=none BUG=none TEST=built for kunimitsu; booted on kunimitsu fab3 and verified with lspci Original-Change-Id: I3b2b8c202b71c2a0c602169841978ed0c4d8bf8d Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292971 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id20e6cafda8664bd0ae3a5acecdd66c58c220694 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27Kunimitsu : FAB3 Adding BoardId supportpchandri
BRANCH=None BUG=chrome-os-partner:44087 TEST=Build and Boot kunimitsu. Original-Change-Id: I30ba8bad69a4fdf8ec29f9eb43a27d2e1c6b93dd Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293832 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8f85547865387091c9a6400611e3314f457076d5 Signed-off-by: pchandri <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/11275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-27Kunimitsu: enable deep S5Naveen Krishna Chatradhi
This patche enables the deep S5 and disables Deep S3. Kunimitsu does not resume from deep S3. This change will unblock the S3 resume path on kunimitsu board. BRANCH=None BUG=chrome-os-partner:42331 TEST=Built and booted on kunimitsu; check s3 works. Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291250 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I07b95a324a27ab658e80674686b47b86412ea097 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-26riscv-trap-handling: Add preliminary trap handling for riscvThaminda Edirisooriya
RISCV requires a trap handler at the machine stage to deal with misaligned loads/stores, as well as to deal with calls that a linux payload will make in its setup. Put required assembly for jumping into and out of a trap here to be set up by the bootblock in a later commit. Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11367 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-08-26inteltool: fix build for FreeBSDRoger Pau Monne
Replace usage of u<bitness> types with proper uint<bitness>_t types. Change-Id: I8359d70304a138b29bfc1358af77af26b2bc8682 Signed-off-by: Roger Pau Monne <roger.pau@citrix.com> Reviewed-on: http://review.coreboot.org/11364 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-26Chromeos: Remove Kconfig workaround for VIRTUAL_DEV_SWITCH warningsMartin Roth
With VIRTUAL_DEV_SWITCH moved under 'config CHROMEOS' in all of the mainboards, this is no longer needed. Change-Id: I5fbea17969f6b0c3b8a5dcd519ab9d36eb2ad6f1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26ChromeOS mainboards: Move more Kconfig symbols under CHROMEOSMartin Roth
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the mainboards that use them. Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-26hp/dl165_g6_fam10/Kconfig: remove unused QRANK_DIMM_SUPPORTMartin Roth
AMD family 10 boards don't use QRANK_DIMM_SUPPORT. Change-Id: Id7e1fba86e2ea1d4d5f5c2e123bd36ad802fd15e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11344 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-08-26Google Kconfig: Add MAINBOARD_HAS_NATIVE_VGA_INIT in good placesMartin Roth
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that are already selecting MAINBOARD_DO_NATIVE_VGA_INIT. Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should not have any other effects. This fixes the warning: warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE || MAINBOARD_HAS_NATIVE_VGA_INIT) Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: move cbfs_file header creation further up the call chainPatrick Georgi
The header is now created before the "converters" are run. Adding new capabilities (and fields to the header) will happen there, so we're close. Change-Id: I0556df724bd93816b435efff7d931293dbed918f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: pass cbfs_file header into "compress" functionsPatrick Georgi
These functions can do all kinds of things, such as converting an ELF image into SELF, or (in the future) compress or checksum entire files. This may require changing or adding fields to the header, so they need to have access to it. The header_size parameter that was provided (but never used) is equivalent to cbfs_file's offset field. Change-Id: I7c10ab15f3dff4412461103e9763a1d78b7be7bb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: drop size argument to cbfs_add_entry_atPatrick Georgi
It's sole use was comparing it to the header's "len" field. Change-Id: Ic3657a709dee0d2b9288373757345a1a56124f37 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: cut down on the debug outputPatrick Georgi
Change-Id: I9a0aad42e4eb67a07c939d7cfa0d2d80838412bb Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: Don't patch cbfs_file->len, it's already set correctlyPatrick Georgi
->len used to be set to the file data length plus the size of the padding used for the cbfs_file header. This isn't the case anymore, so no patching of this field is necessary anymore. ->offset still needs to be patched in that case because its final value can only be determined when the file's actual location is known. Change-Id: I1037885f81b4ed3b68898dd7d0e515cf7a9c90a8 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: drop unused arguments in internal functionPatrick Georgi
Change-Id: Ie4edc5f9c96ffba7dcf8b974c56851658b9538e4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: start moving cbfs_file header creation up the call chainPatrick Georgi
Up to now cbfstool creates the cbfs_file header at the latest possible time, which is unsuitable when the idea is to add further fields to it that need to be configured earlier. Thus, have it ripple up the call chain. Change-Id: I7c160681c31818bc550ed2098008146043d0ee01 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26cbfstool: more descriptive variable namePatrick Georgi
"target", for what? It's the offset where the file header of the currently added file will be located, name it as such. Change-Id: I382f08f81991faf660e217566849773d9a7ec227 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-26crossgcc: rename source file names from gcc-5.2.0/* to binutils-2.25/* in ↵Jonathan A. Kollasch
binutils riscv patches Followup-To: I6f37748b4cf0852d292f8f5156fc27ab8fd481b6 Change-Id: Ib6599b2380b5f2efd92ae78b72b45f3d65681379 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/11329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-08-26buildgcc: Move a bunch of code into a functionzbao
Refactor the code to be better understandable. Change-Id: Ia815a27f7cc83c226a32e87485d712a5fbf4168e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-25xcompile: Force localization of objdump to CMartin Roth
In testing other localization changes, I found that I couldn't build anymore because xcompile wasn't picking up my toolchain. I traced it to the regex comparison of '.*format \(.[a-z0-9-]*\)' to the string 'formato del fichero elf32-i386'. Forcing the localization of objdump to C before doing the comparison fixes the issue. Change-Id: I6bed5a9824807dd5bc5a38b711ab47e2af4b0c29 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11304 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2015-08-25util/kconfig: add olddefconfig targetMartin Roth
There doesn't seem to have been an olddefconfig target in the coreboot version of the Kconfig makefile. It's listed in the .PHONY, but it doesn't seem like it's ever been there. This is useful for expanding a miniconfig saved with 'make savedefconfig'. Change-Id: I3798f8469135b58d32da68d4b0e434ab5351b501 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11273 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-25x86: Get rid of empty loadable segment warningMartin Roth
When the check for global symbols in romstage happens, if everything is good, a warning appears, telling us that the segment is empty. While the empty segment is good, the warning is distracting: "BFD: build/cbfs/fallback/romstage_null.debug: warning: Empty loadable segment detected, is this intentional ?" This change hides that particular warning, but shouldn't hide any other output from objcopy. Change-Id: If22489280712d02a61c3ee5e0cb2a53db87d6082 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11302 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-24crossgcc: rename source file names from empty/* to gcc-5.2.0/* in riscv patchesPatrick Georgi
Some patch implementations (eg. BSD) create new files by taking the "---" file name instead of the "+++" one, so set both to the file name that is to be created. Change-Id: I6f37748b4cf0852d292f8f5156fc27ab8fd481b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reported-by: Idwer Vollering <vidwer@gmail.com> Reported-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/11303 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-23AMD Kconfig: Remove QRANK_DIMM_SUPPORT from unsupported platformsMartin Roth
The AMD K8 northbridge uses the Kconfig symbol QRANK_DIMM_SUPPORT, but the symbol was used on a number of Family 10 boards as well. AMD Family 10 doesn't use this Kconfig symbol for anything. I verified that the symbol wasn't used actually getting used in any of these platforms. Fixes Kconfig warnings for these 19 mainboards: warning: (BOARD_SPECIFIC_OPTIONS...) selects QRANK_DIMM_SUPPORT which has unmet direct dependencies (NORTHBRIDGE_AMD_AMDK8) Change-Id: I454992a4975566fd6439a21f5a800d0cfa1b4d3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11300 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-21soc/intel/common: CACHE_MRC_SETTINGS doesn't depend on HAVE_MRCMartin Roth
The FSP platforms use CACHE_MRC_SETTINGS without setting HAVE_MRC, which caused a Kconfig warning. Since CACHE_MRC_SETTINGS doesn't really depend on HAVE_MRC anymore, remove the dependency in Kconfig. Fixes Kconfig warnings: warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_SETTINGS which has unmet direct dependencies (SOC_INTEL_BROADWELL && HAVE_MRC || SOC_INTEL_COMMON && HAVE_MRC) Change-Id: Id1c108f73d19cbd53b91e1671d57e7752be5d96d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-21crossgcc: Fix x86_64-elf target's -m16 supportPatrick Georgi
It still needs to pass --32 (yes, 32) to the assembler. x86_64-linux does this (through some other config file), x86_64-elf did not. This fixes building SeaBIOS with our x86_64-elf multilib compiler. Change-Id: Ibe2a70e46e64e71c947482be5ec0eaf7f7bf300d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11289 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-20mainboard: Get CHROMEOS/MAINBOARD_HAS_CHROMEOS right (again)Alexandru Gagniuc
CHROMEOS is a user-visible bool. It must not be 'select'ed in Kconfig. That's why we have MAINBOARD_HAS_CHROMEOS. This is the fifth time I find this being used wrong. Why is this confusing/so hard to get right? Change-Id: Icb4629355c63508f5a044b46842524b3d203c2da Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11290 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-20crossgcc: Update gcc to 5.2.0Patrick Georgi
All compilers built, incl. x86_64-elf as multilib and riscv-elf. Change-Id: Iafa61b1d2ffc9c737ab67a417c62417593b69372 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10975 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19libpayload: Fix default_memmove() implementationNico Huber
If I wanted to fill the whole memory address space with one byte, I wouldn't try it that subtle. With size_t beeing unsigned the loop condition >= 0 was always true. Change-Id: Idee6a4901f6697093c88bda354b5e43066c0d948 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11286 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-19Store the payload config and revision in CBFSMartin Roth
Store the payload config and version files in CBFS if using a SeaBIOS or filo payload if INCLUDE_CONFIG_FILE is enabled. Change-Id: I0c1b4da8f6179b9cee06cecfa76bc631b43196e0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10607 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-19Skylake: update cbmem_topRizwan Qureshi
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory regions reserved by fsp for chipset use. With that being removed, the function needs to properly walk though the memory map resulted from fsp memory init to find out the usable address for cbmem root. Refer the FSP 1.3.0 Integartion guide for more details on the Memory Map. systemagent should also use the same mechanism to create the reserved RAM resource. BRANCH=None BUG=None TEST=Build and Boot kunimitsu (FAB3) CQ-DEPEND=CL:*226035,CL:*226045,CL:291573 Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291611 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com> Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: http://review.coreboot.org/11239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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