summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-11-07autoport: Fix nil pointer deref when run without bd82x6xMaximilian Schander
When autoport is run on a system without supported southbridge it won't populate the coresponding data structure. By sanitiy checking after PCI detection autoport can exit cleanly and provide a sufficient error message. Error was: panic: runtime error: invalid memory address or nil pointer dereference [signal SIGSEGV: segmentation violation code=0x1 addr=0x30 pc=0x4be595] goroutine 1 [running]: main.FIXMEEC(0xc42014af80, 0x14, 0xc42014afe0, 0x1a, 0xc4200a914f, 0x4, 0xc4200a916f, 0xf, 0xc420149e60, 0x28, ...) /coreboot/util/autoport/ec_fixme.go:14 +0x105 Change-Id: I6b0fcda76d33b0d3a0379c279f492160ce5add84 Signed-off-by: Maximilian Schander <maxschander@googlemail.com> Reviewed-on: https://review.coreboot.org/22203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07RISC-V boards: Stop using the config stringJonathan Neuschäfer
RISC-V is moving towards OpenFirmware-derived device trees, and the old functions to read the config string don't work anymore. Use dummy values for the memory base and size until we can query the device tree. Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: Use a separate trap stackJonathan Neuschäfer
This is the lazy solution, as explained in the comment, but it works for now. Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: gettimer: Don't use the config stringJonathan Neuschäfer
Accessing the config string doesn't work anymore on current versions of spike. Thus return dummy pointers until we have a better solution. Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: Drop mret workaroundJonathan Neuschäfer
Our toolchain can compile mret now, and once the encoding changes, we'll have to adjust the code anyway. Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: mprv_read_*: Mark result as earlyclobberJonathan Neuschäfer
This fixes a case of mstatus corruption, where GCC generated code that used the same register for the mprv bit and the result. GCC inline assembly register modifiers are documented here: https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07arch/riscv: Fix return type of mprv_read_u64Jonathan Neuschäfer
Change-Id: I3dc12feefe5f0762e27d2ad0234371e91313c847 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07lib/ramtest: Add commentPatrick Rudolph
Add a comment about the tested RAM region size. Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07ec/lenovo/h8: Clear EC output queue before enablementBill XIE
Sometimes (observed on Thinkpad T400s during cold boot) a few (only one observed) garbage bytes may detained in the output queue of EC after power up, and they should be cleared otherwise later communications will be disrupted. Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/22181 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07ec/acpi: add mechanisms to clear EC output queueBill XIE
EC's output could be considered as a queue, and sometimes (observed on Thinkpad T400s during cold boot) a few (only one observed) garbage bytes may detained in such queue after power up. Those garbage bytes should be checked and discarded first before real interactions, otherwise they may disrupt the interaction during EC's enablement, causing a locked rfkill. Change-Id: Iee031306c02f5211a4512c6b4ec90f7f0db196ae Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/22180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07Microcode: add dependency to header filesJulien Viard de Galbert
When using microcode header and updating the header (due to a new release of microcode during early development) the build system doesn't detect the header change. This commit fixes this by adding the appropriate dependency. Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/22307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07Makefile.inc: Cosmetics: Format blobtool commands similar to other toolsDenis 'GNUtoo' Carikli
Change-Id: Iddb09d0838da119bfccd5443652ca7a6baa95c7b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/22126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-07cpu/intel: Add Intel FCBGA1023 socket supportHal Martin
This socket is used by 2nd and 3rd generation mobile SKUs from 2011-2013. select SSE2 per review suggestion Change-Id: I9306a3364ae15530c99ca3379cfa2057c5879681 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-06soc/amd/common/psp: Require PSP PCI definition in SOCMarshall Dawson
Remove the definition for the PSP PCI device from the common PSP code. Any APU using this source should have its own definitions, and this allows for the device to move within the config space. Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06gru: Fix and export SPK_PA_EN GPIO for ScarletJulius Werner
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On Scarlet, we instead moved the audio codec enable (previously on GPIO1_A2) there. Unfortunately the code still had some hardcoded leftovers that were overlooked in the initial port and make our speakers smell weird. This patch fixes the incorrect GPIO settings and adds the speaker enable pin to the GPIOs passed through the coreboot table, so that depthcharge doesn't have to keep its own definition of the pin which may go out of sync. Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-06endian: Fix bebitenc() to actually encode big-endianJulius Werner
bebitenc() just runs a downward loop over the same body as lebitenc(). That doesn't give you a byte-swapped result, it gives you the same final value, just starting from the other side to fill it in. (Also, it confused i++ and i--, so it really gives you a compiler error.) The correct code needs to have the array index inverted relative to the bit shift index to produce a big endian result. Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06intel/cannonlake_rvp: enable CNVi bluetoothBora Guvendik
Enable USB2 port 10 for CNVi bluetooth. TEST=Boot to OS, verify bluetooth functionality. Change-Id: I5f2390c149bf0de911efac09f54ccd641f51bbcd Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-11-06soc/amd/stoneyridge: consolidate addresses in iomap.hAaron Durbin
Take the existing scattered around address space defines and put them in iomap.h. Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-06soc/amd/stoneyridge: start header file for iomapAaron Durbin
Create a new header file, iomap.h, which serves as a single place for providing the address space definitions. Remove the amd_defs.h file that had a single define in it. Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-06mainboard/google/coral: Override VBT selection for astronautren kuo
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms) CQ-DEPEND=CL:*496012 BUG=b:67756548 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I580567decfccd78366c37181255015ac2cd76493 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-05util/docker: add support for crossgcc building paramsPiotr Król
In some cases users may want to build just one toolchain not all. This patch introduces COREBOOT_CROSSGCC_PARAM, which by default is set to all_without_gdb so previous behavior is not changed. Users can pass different parameter eg. COREBOOT_CROSSGCC_PARAM=build-x64 to build just x64 SDK. Change-Id: I858ba09644b5b86a4b0e828e4f342aee5083be93 Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/22276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-04ec/lenovo/h8/acpi/thermal: Add ACPI fan controlPatrick Rudolph
Disengage the fan 10 degree below passive threshold as the automatic EC fan control does not disengage the FAN even when CPU starts melting ... * Add EC registers FAND and FANA. * Add ACPI methods _AC0 and _AL0. * Add fan device and PowerResource for fan control. Tested on Lenovo T430: * The fan disengages at 80°C and keeps running at full speed until temperature drops below 80°C. * Fan can be disengaged using sysfs: /sys/devics/virtual/thermal/cooling_device0/cur_state Tested on Lenovo T500: * The fan disengages at 80°C and keeps running at full speed until temperature drops below 80°C. * Fan cannot be disengaged using sysfs, but the current state can be read: /sys/devics/virtual/thermal/cooling_device0/cur_state Change-Id: I075ff5c69676927db1c5e731294e18796884f97e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21227 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04ec/lenovo/h8/acpi/thermal: Add support for passive coolingPatrick Rudolph
The ACPI spec requires _TSP, _TC1, _TC2 and _PSL for passive cooling. _TSP already has been added in a previous commit. Copy the coefficients used on google devices to activate the feature. Tested on Lenovo T430: The CPU is throttled once the passive threshold has been reached. Tested on Lenovo T500: The CPU is throttled once the passive threshold has been reached. Change-Id: I922923a9029de77158988ac254bab4aad9536935 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-04cpu/intel/speedstep: Emit PPKG object for first packageNico Huber
Tested on Lenovo Thinkpad T500. Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04arch/x86/acpigen: Add function to write a CPU packageNico Huber
Emits a list of CPU cores, e.g. Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 }) Tested on Lenovo Thinkpad T500. Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04mainboard/google/kahlee: remove unused FILECODE macroAaron Durbin
From what I can tell FILECODE isn't used at all in this file. Remove it. Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/stoneyridge: don't open code known literalsAaron Durbin
We have macros for register addresses. Use it for MMIO_CONF_BASE instead of duplicating a literal again. Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/stoneyridge: fix incorrect constants in macrosAaron Durbin
Hex constants need '0x' prefix. Clearly these weren't being used, but they should be fixed properly. Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/stoneyridge: remove superfluous NULL field initializationAaron Durbin
By definition in C, fields that are not explicitly initialized will be zero'd out. Therefore, remove the redundant struture field initialization. Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/common: remove superfluous NULL initializers on globalsAaron Durbin
Global variables that are unitialized in C programs reside in the .bss section. By definition, this section is cleared to 0. Therefore, remove the explicit NULL initialization because it's completely unnecessary. Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/common: remove use of LibAmdMemFill()Aaron Durbin
memset() exists for a reason. There's 0 reason to duplicate the functionality but add extraneous parameters that do nothing. This is just poor coding practices. Remove LibAmdMemFill() usage. BUG=b:62240746 Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/intel/cannonlake: Add DSP supportLijian Zhao
Add dsp driver support for cannonalake, especially the scan_bus function of Audio controller required. TEST=N/A Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04soc/intel/cannonlake: Install common i2cLijian Zhao
Add common i2c support for cannonlake. TEST=N/A Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04src/mainboard/glkrvp: Fix ec_in_rw and wpShaunak Saha
Change-Id: I513b26d39973d9714b531d1ab0755c66d19eb332 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04soc/intel/apollolake: Fix nhlt blobs path for GLKHannah Williams
Change-Id: Iabea32654918575c952857145ee6edb165899baf Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04cpu: assume SSE if SSE2 is selectedAaron Durbin
If the SSE2 Kconfig option is selected also select SSE. Change-Id: I6ccba57d5ae13b8066f2f744cd739282ffd4fe73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04commonlib/helpers.h: Include stddef.hJonathan Neuschäfer
The definition of offsetof() uses size_t, which is declared in stddef.h, according to POSIX. Include stddef.h directly to avoid relying on implicit inclusion. Change-Id: I221be02c332de55c9fcf7d86673709ed43dd5c3c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22230 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Schander <coreboot@mimoja.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04soc/intel/skylake: Update coding style for i2cLijian Zhao
From comment from https://review.coreboot.org/#/c/22238/, the coding style need to be update. TEST=N/A Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04include: Deactivate timestamp_get if kconfig option not setPhilipp Deppenwiese
If CONFIG_COLLECT_TIMESTAMPS not set all timestamp functions should be deactivated by using a pre-processor statement. Change-Id: I8ac63ba7e4485e26dc35fb5a68b1811f6df2f91d Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04asus/p2b: Move to EARLY_CBMEM_INITKeith Hui
Change-Id: I0bf4d6318ade6e931db4f8b1af08db1f9f93c313 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-11-04soc/intel/apollolake: Move to common dsp driverLijian Zhao
Move dsp driver implementation to common dsp driver. TEST=Boot up and check dsp driver loaded or not in OS. Change-Id: Ia2be1c9f18e0e110600bd56a0b6cb8d40ca5e01f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04soc/intel/common: Add common dsp driverLijian Zhao
Audio DSP pci driver can be common across different platforms. TEST=N/A. Change-Id: Ia9206657864b8795799dc71af54996017c1eec57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-03mainboard/intel/cannonlake_rvp: enable SD cardBora Guvendik
Set SCS SD enable FSP parameter and set card detect gpio information. Change-Id: Ic99466c0d2d59070418d765442ff6d217023803b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03intelmetool: Print colored capabilitiesMaximilian Schander
In general more ME capabilities are considered harmfull, useless or unwanted. Therefore an easy overview can be obtained by coloring in red and green. Taken from Change with id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a Add bootguard information dump support https://review.coreboot.org/#/c/16328/ Change-Id: Ia911cc935d512174399aaf93bba982e071942212 Signed-off-by: Maximilian Schander <maxschander@googlemail.com> Reviewed-on: https://review.coreboot.org/22217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-03intelmetool: Do small cosmetic changesMaximilian Schander
Refining some of the code indentations and cosmetics to build upon and import some in-review changes. Change-Id: I0038a146bd899f150518c4832258a42792abaabb Signed-off-by: Maximilian Schander <maxschander@googlemail.com> Reviewed-on: https://review.coreboot.org/22216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-03southbridge: Remove trailing space in `dump_south()` outputPaul Menzel
Change-Id: I4df9f8ce1058a2bb219508d0c8d04e153d37131c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/5179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-03soraka: update pad reset config of WLAN_PE_RST to RSMRSTDivya Chellap
In skylake based platforms, setting GPIO pad reset config to DEEP will reset the gpio configuration across warm reset, set it to RSMRST to preserve the configuration across warm resets. Also, moving the configuration from early to late as appropriate. BUG=b:64386481 BRANCH=none TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot. Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03google/reks: override USB2 Phy settings on BSW D-Stepping SOCMatt DeVillier
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings... Base on Intel recommendation, override following settings for USB2 port 1/2/3 on BSW D-stepping SOC. 1. Set USB[1] register for right side to 7321 2. Set USB[2] register for left side to 7021 3. Set USB[3] register for CCD to 7021 Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03google/reks: override RX ODT limit, RAM geometry if neededMatt DeVillier
Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit... Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107. Use get_ramid() to determine if override is necessary. Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605 Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Original-Reviewed-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 02:20:06 +0000