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2021-02-10mb/google: order matters in mem_parts_used.txtPaul Fagerburg
* Add comments to mem_parts_used.txt to point out that the order of the entries matters when assigning IDs, so always add a new part to the end of the file. * Update existing mem_parts_used.txt to add the same comment. * No updates to Zork variants, because they use an optional ID, so the order actually doesn't matter there. BUG=b:175898902 TEST=create a new variant of dalboz, trembyle, volteer, waddledee, or waddledoo, and observe that mem_parts_used.txt has the new verbiage. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-02-10soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statementFelix Held
This also aligns Stoneyridge with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne: Add verstage supportRaul E Rangel
Setup the config required to support verstage. The offsets are the same as picasso. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-10soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDRFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b6362a9eb2344293dad22357651f646774af789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block/psp: factor out soc_get_psp_base_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPIRaul E Rangel
Required so we pass SPI information down to depthcharge. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd/common/blocks/lpc: Remove common SPI registersRaul E Rangel
Use the SoC versions instead. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/cezanne: Add SPI registersRaul E Rangel
These are identical to picasso. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/picasso: Add SPI registersRaul E Rangel
The picasso SPI registers are different than the ones defined in amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the PSP_SPI_MMIO_SEL bit has been added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/stoneyridge: Add SPI registersRaul E Rangel
This is a copy/paste of amdblocks/lpc.h. The registers are different for picasso and cezanne, so I'm moving them to soc. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10sb/intel/bd82x6x/acpi: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10mb/google/poppy/var/baseboard: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50321 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/intel/skylake: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10mb/intel/wtm2: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10soc/intel/skylake/acpi: Add PEP tableBenjamin Doron
PEP table is applicable to Skylake platform as well. It is required to make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix hooks. Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U), intel_pmc_core kernel module is loaded and reports statuses predictably via debugfs. Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block: Fix guards for PSP transfer bufferRaul E Rangel
The transfer buffer is only required when using VBOOT_STARTS_BEFORE_BOOTBLOCK. The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK or VBOOT_STARTS_IN_BOOTBLOCK. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinbozKevin Chiu
EDGE IRQ from TS might be invalid to HOST, configure IRQs as level triggered to prevent TS lost. BUG=b:179594439 BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TS is functional Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/google/zork/var/shuboz: Adjust touchscreen settingsKane Chen
Modify GPIO_140 delay time and add "disable_gpio_export_in_crs" to meet touchscreen controller power on sequence. BUG=b:174442484 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.cFelix Held
southbridge.c was renamed and split into early_fch.c and fch.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne/chip: add empty set_mmio_dev_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/cezanne/chip: add empty cpu_bus_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google/zork/var/shuboz: Modify touchpad setting for JelbozKane Chen
Since Jelboz support number pad, due to one single coreboot for both Jelboz and Shuboz, modify "overridetree.cb" setting to number pad support for Jelboz. BUG=b:174964012 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-10soc/amd/block/psp/psp: raise log level of PSP failure messagesFelix Held
If the PSP didn't like a command this should be at least a warning on the console and not just a debug message. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntaxElyes HAOUAS
Also, fix typo on "success". Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'. Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10sb/amd/pi/hudson/acpi/fch.asl: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/intel/broadwell/pch: Simplify PCI RMW operationsAngel Pons
This reduces the differences between Lynx Point and Broadwell. Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10nb/intel/i945: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I33c17f56eac0277a12b32af777e2e1ceb086685f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10soc/intel/broadwell: Use common MADT codeAngel Pons
Save for some cosmetic differences, the code is equivalent. Change-Id: I48d4b522009eee9053d247217ca03d8bfea80cdf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10soc/intel/broadwell/pch: Drop `acpi_sci_irq` functionAngel Pons
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using common MADT code on Broadwell, hardcode it as 9 everywhere. Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-10coreboot_table: Use precision when printing lb_gpio nameJulius Werner
The lb_gpio coreboot table entries use name fields fixed to 16 bytes. GCC will not allow creating a static initializer for such a field with a string of more than 16 characters... but exactly 16 characters is fine, meaning there's no room for the terminating NUL byte. The payloads (at least depthcharge) can deal with this as well because they're checking the size when looking at that table entry, but our printk("%16s") does not and will happily walk over the end until somewhere else in memory we finally find the next NUL byte. We should probably try to avoid strings of exactly 16 characters in this field anyway, just in case -- but since GCC doesn't warn about them they can easily slip back in. So solve this bug by also adding a precision field to the printk, which will make it stop overrunning the string. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-10mb/intel/adlrvp/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10mb/emulation/qemu-q35/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-10mb/gizmosphere/gizmo2/bootblock.c: Remove unused includesElyes HAOUAS
Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10mb/google/volteer/var/voxel: Add settings for noise mitgationSheng-Liang Pan
Enable acoustic noise mitgation for volteer platforms. BUG=b:179328166 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-10soc/intel/{cnl,skl}: Add alignment check for TSEG base and sizeBenjamin Doron
Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG base and size) to remaining SoCs. Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/google/volteer: Enable external bypass, clkgate & phygateShreesh Chhabbi
This change sets the soc config options for external_bypass, external_clk_gate and external_phy_gate. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi
This change uses the following information to determine the appropriate S0ix states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13): 1. SoC - UP3 v/s UP4 2. H/W design - external phy gating, external clk gating, external bypass 3. Devices enabled at runtime - CNVi, ISH In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document. Deepest state expected on tigerlake up3 based platforms is S0i3.2. BUG=b:177821896 TEST=Build coreboot for volteer. Verify that deepest S0ix substate that is enabled is S0i3.1 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google/zork: devicetree: Fix typo in *Coprocessor* in commentPaul Menzel
Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants) Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-10acpi: Fix Coverity Scan reportLijian Zhao
Fix the issue that return value "r" in line 534 will get overwritten problem. BUG=CID 1445995 TEST=Build sucessful and boot up in QEMU Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-10src: Remove unused <boot_device.h>Elyes HAOUAS
Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Set Port C VREF as per EEPROM configAngel Pons
Configure Port C VREF according to the settings in the EEPROM. Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Configure 'internal audio'Angel Pons
Implement `mainboard_azalia_program_runtime_verbs` to configure the Realtek ALC888 codec according to the settings in the EEPROM. The encoding of the `internal_audio_connection` field is: 0: Disabled 1: Front HP out 2: Internal speaker Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-06 19:39:07 +0000