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2021-03-15tests: Add lib/memrange-test test caseJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If30a238d32326ffd1d6719470deedc77f176ac72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENHhao_chou
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:175519097 BRANCH=firmware-volteer-13672.B TEST=build and verify on a Copano Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/shadowmountain: Add ACPI entry for BT reset GPIOAamir Bohra
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15mb/google/volteer: Add WiFi SAR table support for Lindar/LillipupKevin Chang
Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:178302811 BRANCH=volteer TEST=build and test no lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-03-15mb/google/volteer/var/lindar: Add FW_CONFIG WIFI_SAR_ID fields in devicetreeKevin Chang
Add FW_CONFIG WIFI_SAR_ID fields in devicetree. BUG=b:178302811 BRANCH=volteer TEST=build and test on lindar/lillipup Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/octopus/var/fleex: Add RTL5682 supportEric Lai
Fleex will use SSFC to support RTL5682. BUG=b:178653122 TEST=abuild Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-03-15mb/google/dedede/var/sasuke: Update LTE GPIO configurationSeunghwan Kim
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence specification. - FCPO (GPP_A10) should not turned off during warm reset. BUG=b:177177967 BRANCH=dedede TEST=Verified LTE power signal waveforms during powering on and off Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15pciexp_device: Rewrite LTR configurationNico Huber
I was bugged by spurious "Failed to enable LTR" messages for years. Looking at the the current algorithm, it is flawed in multiple ways: * It looks like the author didn't know they implemented a recursive algorithm (pciexp_enable_ltr()) inside another recursive algorithm (pciexp_scan_bridge()). Thus, at every tree level, everything is run again for the whole sub- tree. * LTR is enabled no matter if `.set_ltr_max_latencies` is implemented or not. Leaving the endpoints' LTR settings at 0: They are told to always report zero tolerance. In theory, depending on the root-complex implementation, this may result in higher power consumption than without LTR messages. * `.set_ltr_max_latencies` is only considered for the direct parent of a device. Thus, even with it implemented, an endpoint below a (non-root) bridge may suffer from the 0 settings as described above. * Due to the double-recursive nature, LTR is enabled starting with the endpoints, then moving up the tree, while the PCIe spec tells us to do it in the exact opposite order. With the current implementation of pciexp_scan_bridge(), it is hard to hook anything in that runs for each device from top to bottom. So the proposed solution still adds some redundancy: First, for every device that uses pciexp_scan_bus(), we enable LTR if possible (see below). Then, when returning from the bus- scanning recursion, we enable LTR for every device and configure the maximum latencies (if supported). The latter runs again on all bridges, because it's hard to know if pciexp_scan_bus() was used for them. When to enable LTR: * For all devices that implement `.set_ltr_max_latencies`. * For all devices below a bridge that has it enabled already. Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/kahlee: remove get_gpe_tableFelix Held
Since no board overrides the weak get_gpe_table function, gpe_configure_sci wasn't called for any variant, so drop the function. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCESTim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the adlrvp mainboard. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0Tim Wawrzynczak
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the brya0 mainboard. TEST=snippet from dmesg logs shows the correct resources being allocated: PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24 PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20 PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24 PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20 PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24 PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resourcesTim Wawrzynczak
The Intel ADL BIOS specification #627270 recommends reserving the following resources for each PCIe TBT root port: - 42 buses - 192 MiB Non-prefetchable memory - 448 MiB Prefetchable memory Add a mainboard Kconfig which will auto-select these recommended values, in addition to PCIEXP_HOTPLUG. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Remove _DSD from tcss_pciexp ASL fileTim Wawrzynczak
The _DSD is generated at runtime using the Intel common pcie driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iee25a77bf5cc6636f46a5c32f3eeabe8524e0a04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51454 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/alderlake: Remove _DSD from tcss_dma ASL fileTim Wawrzynczak
The _DSD is generated at runtime using the Intel common USB4 driver, therefore remove it from the ASL files. BUG=b:182522802, b:182478306 TEST=boot into latest kernel, no thunderbolt driver errors seen Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/blipper: Enable touchpad supportZanxi Chen
Add touchpad into devicetree for blipper. BUG=b:172787208 BRANCH=dedede TEST=built blipper firmware and verified touchpad function the kernel log: found RMI device, manufacturer: Synaptics Change-Id: I2c9b61ba9d282f994e2f756bafe4af1091d4d617 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51188 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons
Done for consistency with other platforms. This also drops redundant S3 resume logging, as `southbridge_detect_s3_resume` already prints it. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons
The `HPET_ADDRESS` Kconfig option has the same value. Use it instead. Change-Id: I268e949d4396aa20e38f719b36cc4e6226efe082 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-15Revert "mb/google/zork: restore stamp_boost parameter to 2500 for dirinboz"Kevin Chiu
This reverts commit 87a1bd696d47f80101e46132efae8cad8cfe5c7e. Reason for revert: skin temperature is overheating due to boost time is too long BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test => pass Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-15soc/mediatek/mt8192: devapc: Add domain remap settingNina Wu
MT8192 devapc supports remapping domains. There may be different domain bit for different subsys. For example, domain bit in INFRA is 4-bit, while in MMSYS, domain bit is 2-bit. For INFRA master to access MM registers, the domain bit will change from 4 to 2 and need to be remapped. In this patch we have remapped: 1. TINYSYS (3-bit to 4-bit) - domain 3 to domain 3 - others to domain 15 2. MMSYS slave (4-bit to 2-bit) - domain X to domain X, for X = 0 ~ 3 - others to domain 0 Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-15mb/google/asurada: get SKU ID from AP strapping pinsHung-Te Lin
The SKU ID for Asurada should come from AP ADC channel 5 and 6. BUG=None TEST=make; boots on asurada Change-Id: I6a00c555f20aca4cd7f8bcee46ee81c17ef6ca3c Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-15mb/google/asurada: revise PMIC and RTC initializationYidi Lin
Move the initialization from bootblock to romstage for following reasons: - Follow MT8183 initialization sequence. - PMIC and RTC functions are only called after verstage. - Reduce bootblock size. - PMIC initialization setting is complex and may need to be changed by an RW firmware update. TEST=boot to kernel successfully Change-Id: I3e4c3f918639590ffc73076450235771d06aae91 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-15Update amd_blobs submodule to upstream masterMartin Roth
Updating from commit id 3b1a734: 2021-03-02 11:51:18 -0700 - (picasso: Update FSP to build 0x26) to commit id 3a9d7cd: 2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware) This brings in 1 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iff3b4ff667f97d3804bc66477f8a95a60e23b1a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51459 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15Update blobs submodule to upstream masterMartin Roth
Updating from commit id 4fdfa1c: 2021-03-05 13:10:22 -0600 - (mb/amd/majolica: Update to use proper APCBs built for Majolica) to commit id fc2d4e2: 2021-03-12 10:31:48 -0700 - (mb/google/guybrush: Add initial APCB) This brings in 1 new commit. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3003fdb8ba0bcfbc33452999c35a9a21775ecc10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-15soc/amd/cezanne: Add i2c controllers to chipset.cbMathew King
BUG=b:180531661 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I5feeead1dcb368c5173901f5cab411f439dffede Reviewed-on: https://review.coreboot.org/c/coreboot/+/51475 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14device/pciexp_device.c: Remove CPP guardingArthur Heymans
Let the linker do its job. This fixes building with !CONFIG_PCIEXP_HOTPLUG on some platforms. Change-Id: I46560722dcb5f1d902709e40b714ef092515b164 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-14mb/google/guybrush: Enable PCIe devices in devicetreeMathew King
BUG=b:181690884 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14soc/amd/cezanne/Kconfig: turn on GOPNikolai Vyssotski
To use this, Enable "CONFIG_RUN_FSP_GOP" in the platform's Kconfig. BUG=b:171234996 TEST=Boot Majolica with GOP graphics Change-Id: Ic9401cc93ee50fb7dbd84fe26ef24306a1673f58 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-14doc/mb/lenovo/montevina: Fix constants for 16MiB flashNico Huber
The current values are actually for 32MiB and result in a brick if used with a 16MiB chip because of the invalid bios region. Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14soc/amd/picasso/mca: don't do out of bounds array accessesFelix Held
The Picasso APUs advertise 23 MCA banks in the lower byte of the IA32_MCG_CAP MSR, which is more than the 7 core MCA banks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e1c8ed437820b350c78b0517e6521582002ee1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-14soc/amd/picasso/mca: fix core MCA bank namesFelix Held
The bank names were copied over from Stoneyridge, but they don't match for Picasso. TEST=Checked the Picasso PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia86cf3874f8b16b007bad46535af6dafb776fbdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/51476 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14payloads/LinuxBoot/u-root: add boot template to u-rootAlexander Couzens
Without the boot template, u-root doesn't include any boot commands. Booting other OS is impossible. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: I7d0742d115715eb40e293e2a8711d1ff20d8970a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51331 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Add SPDs into buildMartin Roth
This enables the standard library method of adding SPDs to CBFS. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14mb/google/guybrush: Enable EM100 support on guybrushMathew King
Add the option to build guybrush firmware with support for EM100. This will assist in bringup of the new board. BUG=b:180723776 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUMERaul E Rangel
Since not all mainboards based on the Cezanne SoC have to support ACPI resume, select this option in the mainboard's Kconfig and not in the SoC's Kconfig. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/amd/cezanne/acpi/soc.asl: Include sleepstates.aslRaul E Rangel
Needed to get the _SX ASL methods. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6323ba413a21d9d867727dbb28340e6df807c86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/intel/common/fast_spi: Fix check-fmap-16mib-crossing checkFurquan Shaikh
Currently, `check-fmap-16mib-crossing` compares the offset and end of each SPI flash region to 16MiB to ensure that no region is placed across this 16MiB boundary from the start of SPI flash. What really needs to be checked is that the region isn't placed across the 16MiB boundary from the end of BIOS region. Thus, current check works only if the SPI flash is 32MiB under the assumption that the BIOS region is mapped at the top of SPI flash. However, this check will not work if a flash part greater than 32MiB is used. This change replaces the hardcoded boundary value of 16MiB with a value calculated by subtracting 16MiB from the SPI flash size (if it is greater than 16MiB). This calculated value is used as the boundary that no region defined in the flashmap should be placed across. The assumption here is that BIOS region is always placed at the top of SPI flash. Hence, the standard decode window would be from end_of_flash - 16M to end_of_flash (because end_of_flash = end_of_bios_region). Currently, there is no consistency in the name used for BIOS region in flashmap layout for boards in coreboot. But all Intel-based boards (except APL and GLK) place BIOS region at the end of SPI flash. Since APL and GLK do not support the extended window, this check does not matter for these platforms. Change-Id: Icff83e5bffacfd443c1c3fbc101675c4a6f75e24 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51359 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/intel/fast_spi/Makefile: Rewrite 16mib check for legibilityNico Huber
Perform some cosmetical changes: * Override the first prerequisite so we can use `$<`. * Add/remove whitspace to align things (recipe needs to be indented by a single tab only). * We can use shell variables inside double quotes. To make the end of the variable name clear, use braces, e.g. "${x}". NB. Most of the double quotes are unnecessary. They only change the way the script would be failing in case of spurious whitespace. * Break some lines doing multiple things at once. * To reduce remaining clutter, put reading numbers into a shell function. And functional changes: * No need to spawn `cat`, the shell can redirect input as well as output (using `<`). * To read a number from the `fmap_config.h`, we spawned 4 processes where a single one can achieve the same. With one exception: GNU awk refuses to parse hex numbers by default. Luckily, it turned out that we don't need intermediate decimal numbers: Shells can do arithmetic with hex values as well. Change-Id: Ia7bfba0d7864fc091ee6003e09b705fd7254e99b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-13soc/intel/fast_spi/Makefile: Fix exit of 16mib-check recipeNico Huber
Currently, if everything worked fine, `$fail` will be unset, leading to the following `if` statement: if [ -eq 1 ] Resulting in the error message: /bin/sh: line 9: [: -eq: unary operator expected Fix this by removing the whole `if`, we can just use `exit`. Change-Id: I1bc7508d2a45a2bec07ef46b9c5d9d0b740fbc74 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-13cbfstool: Add support for platform "fixups" when modifying bootblockJulius Werner
To support the new CONFIG_CBFS_VERIFICATION feature, cbfstool needs to update the metadata hash embedded in the bootblock code every time it adds or removes a CBFS file. This can lead to problems on certain platforms where the bootblock needs to be specially wrapped in some platform-specific data structure so that the platform's masked ROM can recognize it. If that data structure contains any form of hash or signature of the bootblock code that is checked on every boot, it will no longer match if cbfstool modifies it after the fact. In general, we should always try to disable these kinds of features where possible (they're not super useful anyway). But for platforms where the hardware simply doesn't allow that, this patch introduces the concept of "platform fixups" to cbfstool. Whenever cbfstool finds a metadata hash anchor in a CBFS image, it will run all built-in "fixup probe" functions on that bootblock to check if it can recognize it as the wrapper format for a platform known to have such an issue. If so, it will register a corresponding fixup function that will run whenever it tries to write back modified data to that bootblock. The function can then modify any platform-specific headers as necessary. As first supported platform, this patch adds a fixup for Qualcomm platforms (specifically the header format used by sc7180), which recalculates the bootblock body hash originally added by util/qualcomm/createxbl.py. (Note that this feature is not intended to support platform-specific signature schemes like BootGuard directly in cbfstool. For anything that requires an actual secret key, it should be okay if the user needs to run a platform-specific signing tool on the final CBFS image before flashing. This feature is intended for the normal unsigned case (which on some platforms may be implemented as signing with a well-known key) so that on a board that is not "locked down" in any way the normal use case of manipulating an image with cbfstool and then directly flashing the output file stays working with CONFIG_CBFS_VERIFICATION.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I02a83a40f1d0009e6f9561ae5d2d9f37a510549a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13cbfstool: Support CONFIG_CBFS_VERIFICATION and metadata hash anchorJulius Werner
This patch adds support for the new CONFIG_CBFS_VERIFICATION feature to cbfstool. When CBFS verification is enabled, cbfstool must automatically add a hash attribute to every CBFS file it adds (with a handful of exceptions like bootblock and "header" pseudofiles that are never read by coreboot code itself). It must also automatically update the metadata hash that is embedded in the bootblock code. It will automatically find the metadata hash by scanning the bootblock for its magic number and use its presence to auto-detect whether CBFS verification is enabled for an image (and which hash algorithm to use). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I61a84add8654f60c683ef213b844a11b145a5cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41121 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Add guybrush APCBs into buildMartin Roth
This adds the Guybrush APCBs into the AMD firmware binary. BUG=b:182510885 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13soc/amd/cezanne/fsp_params.c: GOP: pass VBIOS pointer to FSPNikolai Vyssotski
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver. BUG=b:171234996 Change-Id: I504f808d85d8084e6f32f73cebf02fb0f784cd73 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-13soc/amd/picasso/fsp_params.c: GOP: pass VBIOS pointer to FSPNikolai Vyssotski
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver. BUG=b:171234996 BRANCH=Zork Change-Id: I49adcacf2abb914e460fbc87b488a22dca8c8af2 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-13soc/amd/common/block/graphics/graphics: GOP: load VBIOSNikolai Vyssotski
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000) since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not set). Add Cezanne GFX PID. BUG=b:171234996 BRANCH=Zork Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-13mb/google/guybrush: Add ACPI support for Chrome ECMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13soc/amd/cezanne: Move globalnvs.asl to the correct locationMathew King
BUG=b:180507937 TEST=guybrush builds without globalnvs in dsdt.asl Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3ffe94f7b575126e61245bed9c9560313df2d725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51291 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Configure eSPI GPIOs in early stageMathew King
BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13mb/google/guybrush: Configure early GPIOs in earliest stageMathew King
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:181961514, b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13mb/google/guybrush: Enable verstageMathew King
BUG=b:181961514 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I289a2ad1adc5dcc33c5863d6138f66b9b6dc6590 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-12util/qemu: Add additional config file for QEMU/Q35Nico Huber
The `q35-alpine.cfg` adds a lot of PCIe devices to resemble the topology inside an Intel Alpine Ridge Thunderbolt controller. By no means could this be detected as such a controller. But having a real-world example of such a topology can help to test the allocator and other algorithms on a deeper tree. It adds two levels of PCIe switches (`alpine-root` and `alpine-1`), and two endpoints (a `pci-testdev` and an xHCI controller). It can be added to the default `q35-base.cfg` config, e.g. with: $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg Change-Id: Ieab09c5b67a5aafa986e7d68a6c1a974530408b0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51329 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 13:27:08 +0000