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2014-05-05baytrail: fix up FADTAaron Durbin
The FADT for baytrail had incorrect offsets leading to the kernel spewing a huge mess of ACPI errors. Fix these offsets to be initialized in the chipset code. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted into kernel on rambi. Login screen comes up. Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175663 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4941 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05baytrail: interrupt routing supportAaron Durbin
This provides the initial support for interrupt routing in bay trail. It includes both acpi changes and board changes to ensure the interdependencies are met with the current ASL code. The PIRQ routing is handled by the mainboard exporting an irqroute.h header that describes the per device and PIRQ PCI settings. There are still a lot of ACPI errors in the kernel with this change, though. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted rambi into kernel. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e Reviewed-on: https://chromium-review.googlesource.com/175700 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05haswell: move to mp_init libraryAaron Durbin
The mp_init library was based off of haswell code, but baytrail was the first chipset to take advantage of it. Move haswell over to using it so that the code duplication can be removed. Change-Id: Id6e9464df028aa6ec138051f925817c85b4c13e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5413 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-05-05lib/hexdump: Use `size_t` for length parameter of `hexdump32()`Paul Menzel
In the signature of the function `hexdump32()` it does not make sense to represent a length, assumed to be positive, as a signed integer. With this change, it is no longer necessary to cast a pointer to unsigned long when passing it to `hexdump32()`. The same change for the function `hexdump()` was done in commit 3dd0e72d [1]. lib/hexdump: Take const void * and size_t as arguments [1] http://review.coreboot.org/4575 Change-Id: Id97f5daff95f94e862ee8b5be896a6629b125a13 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5646 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05lib/hexdump.c: Indent with tabs instead of spaces and remove empty linesPaul Menzel
The coding style requires to use tabs for indentation and not spaces. Use GNU indent 2.2.11 with the switch `-linux` to indent the file, which also removes the empty lines at the end of the file. Change-Id: I874f178e50d7558d3299026aec2771ad45f88d8e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4576 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Fix BiosCallouts table formattingKyösti Mälkki
Already done for fam15tn and fam16kb. Change-Id: I3da36bfe6fd1805867eee5aa1f017c4fda084349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA: Implement EmptyHeap()Kyösti Mälkki
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear the fields individually. Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5659 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Use common calloutsKyösti Mälkki
Backported from fam15tn and fam16kb. This also implements GetHeapBase() to satisfy some requirements of HAVE_ACPI_RESUME for the following boards: amd/inagua amd/south_station amd/union_station asrock/e350m1 Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5658 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam14: Add fam14_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5657 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05jetway/nf81-t56n-lf: Revert change on function prototypesKyösti Mälkki
These function prototypes to remain identical across all AGESA families. Change-Id: If2a0a08fa7122e6becded37d032d3c40bde2d149 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add GetHeapBase()Kyösti Mälkki
While fam15 boards do not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add GetHeapBase()Kyösti Mälkki
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this from fam14. Implementation of this function is common across different families. Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15tn: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam16kb: Use common GetHeapBase()Kyösti Mälkki
Implementation of this function is common for all boards in family, and also across different families. Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Use common calloutsKyösti Mälkki
Backport from fam15tn and fam16kb. Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam15: Add fam15_callouts headerKyösti Mälkki
Backported from fam15tn and fam16kb. Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Move dimmSpdKyösti Mälkki
Implemented under northbridge/ on other families. Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AGESA fam12: Add fam12_calloutsKyösti Mälkki
Although amd/torpedo is only fam12 board at the moment, backported this from fam15tn and fam16kb. Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05AMD F14h boards: Sanitise headers in agesawrapper.cEdward O'Callaghan
Change-Id: Ic9c5e8abb3da020a642635ee74c9242091923619 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5628 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05AMD F14h boards: Use std memset/memcpy func over AGESAEdward O'Callaghan
In amd/{persimmon,inagua} and derived boards avoid using AGESA reimplementation of memcpy as following the reasoning in: e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA Change-Id: I943b46103c3bf1c5fd88b25e9f9595b9adfcafeb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5625 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05lenovo/t60: Move mainboard_enable() code into a mainboard_init()Trevor Mosey
mainboard_enable() is now modelled after google/parrot where the enable function only sets dev->ops->init for the root device to point to a mainboard_init() function, which in turn is called in a later pass over the device tree to do the actual initialization. Change-Id: I89a5192bd45ca8321b2b1ac49b073122e0f6ee2b Signed-off-by: Trevor Mosey <uberushaximus@gmail.com> Reviewed-on: http://review.coreboot.org/5637 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03AMD: Drop redundant test for CONFIG_RAMTOPKyösti Mälkki
Same test is already done in x86/mtrr.h. Change-Id: Ib0785d047567374294b9ee7afc4f4244f9ced926 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5620 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Drop useless mainboard-romstage definesPatrick Georgi
Some src/mainboard/*/*/romstage.c files use defines which later modify the behaviour of included .c files. Since it's a pain to work out what is affected by these, drop values that are only defined in the board but never used, or defined to identical values as in spd.h (and use that one instead). Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5639 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03build: allow building crossgcc when .config existsPatrick Georgi
Under some circumstances the coreboot toolchain test prevented building crossgcc, which is counter-productive: If a .config file exists but no suitable .xcompile. Don't assume anything about the tree when building crossgcc or crosstools targets. Change-Id: I4d6e7a88908dc967342daf30df0fcbcc269ae63d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5584 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-03Move redundant Makefile rules from arch to top level.Furquan Shaikh
Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others from arch level Makefile.inc to top level Makefile.inc. Also, organize Makefile.inc at arch level into per-stage rules and variables. Change-Id: I7dc5b2d31c959b55bb92d9c7811427c4dada1db5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5571 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payloadPaul Menzel
If the user selects GRUB 2 as the payload in Kconfig, coreboot does not need to initialize the PS/2 keyboard as GRUB 2 is going to do it. Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payloadPaul Menzel
As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is able to initialize the PS/2 keyboard itself, so it is not necessary to let coreboot do it. SeaBIOS is also able to do it faster as discussed in a thread on the coreboot mailing list from October 2010 [1]. In that thread it was also proposed to not let coreboot initialize the PS/2 coreboot when SeaBIOS is used as a payload. [1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310 subject: [coreboot] coreboot+seabios timings Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboardPaul Menzel
Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02qemu-armv7: Kconfig cleanupKyösti Mälkki
RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7. Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02asrock/e350m1: Sanitize #includesEdward O'Callaghan
Following similar reasons as: 5ff4b08 jetway/nf81-t56n-lf: Sanitize #includes Change-Id: Ie88b884bc2d4481bc2583d5be1f4d1376547f3c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5614 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2014-05-02jetway/nf81-t56n-lf: Set OEM to Jetway in DSDT and mptablesEdward O'Callaghan
Jetway builds this hardware, so let us be sure to set the truth in the DSDT Definition block and MPTables. Change-Id: I2dfb89152aa3b895ec6975293c5a5998ab6b52bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02arch/x86/boot: Indent mpspec.c and make a loop more legibleEdward O'Callaghan
Fix some space->tab style and a for-for loop embedded to be more understandable/readable. Change-Id: I740c544e8c9330e6efbbd66a5c1e6a4a33d1a75e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5631 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02asrock/e350m1/devicetree.cb: Correctly indent device linePaul Menzel
Fix up commit dfa8a32f [1]. src/mainboard/asrock/e350m1: Properly indent devicetree.cb [1] http://review.coreboot.org/5612 Change-Id: I59b3ec2f00d69951aa8a96c4a9c3de5b219acbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5619 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cbEdward O'Callaghan
Following the reasoning in, dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5629 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02superio/winbond/w83627thg: Remove w83627thg_enable_serial symbolEdward O'Callaghan
Remove model specific implementation, w83627thg_enable_serial, from romstage component of sio support. Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5604 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02mainboard/*: Use generic winbond romstage in place of w83627thgEdward O'Callaghan
Use the generic implementation of winbond in place of the model specific w83627thg_enable_serial() as so that it maybe removed later. Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5603 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01Build without ChromeOSKyösti Mälkki
Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3978 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01ChromeOS: Use common fill_lb_gpio()Kyösti Mälkki
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01device: Conditionally bypass oprom executionKyösti Mälkki
Builds with CHROMEOS can bypass VGA oprom when boot is not in developer or recovery modes. Have the same functionality available without CHROMEOS but with BOOTMODE_STRAPS. Change-Id: I97644364305dc05aad78a744599476ccc58db163 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5595 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01ChromeOS: Remove oprom_is_loadedKyösti Mälkki
A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01google/stout: Fix build without ChromeOSKyösti Mälkki
Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01Declare recovery and developer modes outside ChromeOSKyösti Mälkki
Move the implementation for recovery and developer modes from vendorcode/google/chromes to lib/. Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01device: provide option to always load PCI option romsKyösti Mälkki
Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5594 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-04-30console: Fix UART selection promptKyösti Mälkki
Without this change, removal of default UART_FOR_CONSOLE entries under mainboard/ Kconfig will remove this option entirely from created .config file. Change-Id: I11422ddb8c51abca177f999936c995ae0c91c459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5626 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-30baytrail: Add default _OSC methodDuncan Laurie
This is needed to let the kernel know it can control everything and not to disable features. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175629 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4939 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add root bus resource regionsDuncan Laurie
Populate the PCI mmio region from NVS TOLM variable. Other regions are fixed. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175628 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4938 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add MCFG table to ACPIDuncan Laurie
This adds the PCI configuration region table to baytrail. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175627 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4937 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Clean up NVS regionDuncan Laurie
There is a lot of NVS allocated to things that are not really used. Most of these are removed and some are moved around. Thermals are expected to be handled with DPTF so I've removed that bit of code but have not yet cleaned up the thermal zone. I left in the SIO BARs since I think we will need those still even though they may need work still. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Id16ee67e6b3709a303c001afd72947147f938127 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175626 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4936 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add function to read top of low memoryDuncan Laurie
The top of low memory is also the start of the region where PCIe resources are allocated. This needs to be passed in ACPI but is only readable from IOSF. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4935 Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 07:16:14 +0000