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2020-09-25soc/intel: Use ASL 2.0 syntax for GPIO ASL helper functionSubrata Banik
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL. TEST=Able to build and boot Hatch, EVE and ICLRVP platform. Dump and disassemble DSDT to ensure GRXS,GTXS etc functions implementation remain unchanged prior and after this CL. Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25soc/intel/{jsl,tgl}: Refactor gpio_op.aslSubrata Banik
Also align GPMO ASL function with TGL. Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-25soc/mediatek/mt8183: Enable CA perbit mechanismHuayang Duan
LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin of some CA PIN window is too small than others. Need to enable the CA perbit mechanism to avoid those risks. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25mb/clevo/cml-u: remove the duplicate WiFi PCIe device in devicetreeMichael Niewöhner
Change-Id: Ibb46bbf0c889bb8b3fd1a4c0331dc719baffc7a2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45678 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25mb/clevo: Rename l140cu to cml-uFelix Singer
In addition to CB:45664, rename clevo/l140cu to clevo/cml-u being able to add more variants under a generic mainboard later. Change-Id: I9c16e24830ebb80752df302aa2e63d9df8edad95 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45665 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24mb/clevo/l140cu: Make usage of variant mechanismFelix Singer
Clevo mainboards can be grouped by their common platform. Therefore, restructure the mainboard directory as a first step, so that the variant mechanism is used. This moves most of the code into the variant dir, since the L140CU is the only variant at the moment. Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24soc/intel/alderlake: Select ACPI_INTEL_HARDWARE_SLEEP_VALUESAngel Pons
This resolves a Kconfig warning regarding unmet dependencies. Change-Id: I9e70a4d333afefcb27c097aa9ce84e5effc0d7c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24soc/intel/cnl: drop lpit.asl in favor of common versionMichael Niewöhner
Drop lpit.asl from CNL and switch to the common one in the three boards currently using it. The only difference between the two is the usage on macros in common code instead of plain integer values. Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-24mb/google/volteer: Enable CnviBtAudioOffloadJohn Zhao
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=b:169045123 TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP configuration. Booted up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naveen M <naveen.m@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffloadJohn Zhao
This change adds configuration support for both of CnviBtCore and CnviBtAudioOffload. BUG=b:169045123 TEST=Built and boot up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Id4bf41f07c4a53de17e9eb91a8ddfb1083cbf83e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45585 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Naveen M <naveen.m@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24mb/google/volteer/var/voxel: Update gpio settings for EVTSheng-Liang Pan
Based on EVT schematic and gpio table of voxel, update gpio settings for voxel EVT. BUG=b:156841729 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Idf88d83ad6d873283eb1eb8a45459ae3e74df124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45173 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24templates: add ddr4-spd-empty.hex to SPD_SOURCESPaul Fagerburg
We need at least one SPD in SPD_SOURCES when creating a new variant of trembyle or dalboz, or else coreboot won't build. Add the empty DDR4 SPD so that we can build the new variant. Add an empty mem_parts_used.txt so that the developer can add the supported memory parts and regenerate spd/Makefile.inc using spd_tools. BUG=b:169199396 TEST=create a new variant of dalboz or trembyle and observe that the build succeeds. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I764690c76529780186d0a1d156a623821f9d6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-09-24soc/intel/common/smbus: Add support for Apollo Lake SoCMaxim Polyakov
Previously, SMBUS support was not required for Apollo Lake, since the SPD was read inside FSP-M, during memory initialization. However, the Kontron mAL-10 COMe module contains Nuvoton HWM chip that is connected to the processor via SMBUS. This patch adds SMBUS common driver support for Apollo Lake to initialize this HWM. TEST = After loading the nct7802 module on the Kontron mAL-10 with Linux OS, we can read the hwm registers, see temperature and fan speed: coretemp-isa-0000 Adapter: ISA adapter Package id 0: +52.0°C (high = +110.0°C, crit = +110.0°C) Core 0: +52.0°C (high = +110.0°C, crit = +110.0°C) Core 1: +52.0°C (high = +110.0°C, crit = +110.0°C) Core 2: +53.0°C (high = +110.0°C, crit = +110.0°C) Core 3: +53.0°C (high = +110.0°C, crit = +110.0°C) nct7802-i2c-0-2e Adapter: SMBus CMI adapter cmi in0: +3.35 V (min = +0.00 V, max = +4.09 V) in1: +1.92 V in3: +1.21 V (min = +0.00 V, max = +2.05 V) in4: +1.68 V (min = +0.00 V, max = +2.05 V) fan1: 0 RPM (min = 0 RPM) fan2: 1729 RPM (min = 0 RPM) fan3: 0 RPM (min = 0 RPM) temp1: +53.5°C (low = +0.0°C, high = +85.0°C) (crit = +100.0°C) sensor = thermistor temp4: +53.0°C (low = +0.0°C, high = +85.0°C) (crit = +100.0°C) temp6: +0.0°C Change-Id: I408ef84ede27a45fb057e22b2757fa6e66277ddd Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44475 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-24mb: Copy system76/lemp9 to clevo/l140cuFelix Singer
Copy system76/lemp9 to clevo/l140cu, since it's a Clevo notebook actually and both have the same mainboard. This commit is meant to create a working copy for clevo/l140cu. The only changes are names. Further patches will follow to make this mainboard more generic. Since system76/lemp9 is based on System76's EC firmware, EC stuff does not work correctly yet. This will be fixed in another patch. Tested on TUXEDO InfinityBook S 14 v5 and PCZ Lafité Pro 14. Change-Id: I7c2993256fd9123a8013df5ba8292ea1ead10f74 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-24soc/intel/alderlake/romstage: Fix compilation issueSubrata Banik
Refer to commit 490546f (soc/intel: rename get_prmrr_size) for details. Change-Id: I4a83feedcdb337ba9613a07215196bc223fb46d1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45651 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/google/zork: simplify flashmap fileFelix Held
Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=None BRANCH=zork Change-Id: I81c121d4fce13a9d2aad4477955cb4770794d244 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23mb/amd/mandolin: simplify flashmap fileFelix Held
Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=Timeless build for amd/mandolin resulted in identical binary. BRANCH=zork Change-Id: I196c7857f165e75b543c1bda650e044b5ad0664e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23soc/amd/picasso: use output of fmaptool to find APOB regionFelix Held
Parse the generated fmap_config.h file instead of the .fmd file supplied by the board to determine the size and location of the APOB region. Parsing the generated file allows to write .fmd files without having to take into account that the shell script part in Picasso's Makefile.inc can only parse a subset of the .fmd syntax. BUG=b:157068645 TEST=Timeless build for amd/mandolin resulted in identical binary. BRANCH=zork Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23util/intelmetool: Fix the BootGuard dump featurePablo Stebler
Read the correct bits for measured and verified boot, print information about some other bits. Signed-off-by: Pablo Stebler <pablo@stebler.xyz> Change-Id: Ie79d6da33032aee94d716bf0698b5501bbc424fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/45516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-23mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVPShreesh Chhabbi
BUG=none TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated. cat /sys/devices/system/cpu/intel_pstate/ Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609 Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu
Configure FSP UPDs for the chipset minimum assertion widths and power cycle duration per mainboard variants. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159108661 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/google/octopus: Set ModPhyIfValue to default value 0x12Marx Wang
0x12 will be more stable according to validation result on SD card and USB devices. BUG=b:163382089 BRANCH=none TEST=check if SD cards and USB devices work properly Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: Ic98f27b6164daa3667009300439c61fed43a4a0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45573 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23util/cbfstool/fmaptool: generate defines for all fmap sectionsFelix Held
Add defines for the start and size of the FMAP sections to the optionally generated header file. For the defines the name of the corresponding FMAP section is used without the full path, since every section name should be unique anyway as documented here: Documentation/lib/flashmap.md BUG=b:157068645 TEST=Generated header file contains expected defines. BRANCH=zork Change-Id: Ie31161cfd304b69a3cb4bb366bf365d979e77c64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23util/cbfstool/fmd: make flashmap_flags bitfield struct elements unsignedFelix Held
One bit wide bitfields should always be unsigned, since they can only be either 0 or -1, but never 1 which is assigned to that bit field in some cases. Making this unsigned allows it to have the values 0 or 1 which is what we want there. BUG=b:157068645 BRANCH=zork Change-Id: I99c236df583528848b455ef424504e6c2a33c5d6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23lib/Makefile.inc: drop redundant conditional on CONFIG_HAVE_SPD_IN_CBFSMichael Niewöhner
Change-Id: I56d13540b2c6b66d5c674ae3d5bab0ac9505df58 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45154 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23mb/dell: Fix uninitialized variables usageJohn Zhao
Coverity detects uninitialized variables through PASS_BY_REFERENCE usage. Fix this issue by initializing variables before their uage. Found-by: Coverity CID 1429765, 1429772, 1429780 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ie583b072a76949fb3f17c1271a6427ee942db0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/45611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-09-23lib/Makefile.inc: fail build when SPD would be emptyMichael Niewöhner
Add a check to be sure that at least one SPD file will be added and fail the build when the resulting spd.bin would be empty. Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45131 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23ec/google/chromeec: set DPTC power parameter at OS startupKevin Chiu
set DPTC power parameter per clamshell/tablet mode after EC OP region is accessible. BUG=b:157943445 BRANCH=zork TEST=1. emerge-zork coreboot 2. power on DUT in tablet mode then check "thermctl_limit" will change automatically Change-Id: Ic3e1119881790c34f5649986334b4e3cecafc02b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-23template/waddledoo: remove acpi/camera.aslPaul Fagerburg
ACPI tables are generated at runtime for camera components. Remove the static ASL file. BUG=b:168755528 TEST=create a new variant of Waddledoo and observe that the build succeeds. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ie9e3d5856d5e95562df03814ab31e4e79a40a968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45629 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/*: drop GENERIC_SPD_BIN from boards without soldered memoryMichael Niewöhner
Drop GENERIC_SPD_BIN from boards selecting it, despite having no soldered memory. Change-Id: Id05fe45007d5662ff9bee326f28470df1206fcff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45146 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/system76/lemp9: gpio: convert gpio.h to a cleaner formatMichael Niewöhner
Convert gpio.h to a compacter, cleaner format by keeping gpios in a single line, where possible. This was done with the following fancy vim regex replacement commands. (Neither sed, nor awk multiline matching syntax are friends with me...) Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before pasting each command, press enter and see how the format changes. g#^\t//#d %s/^\t\t/\t/ g/PAD_.*$\n\n[^/]/s/\n// g#// NC#d %s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g %s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */ %s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */# Finally some indents and multiline comments need to be fixed manually. Test: images built with TIMELESS do not differ. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-22nb/intel/ironlake: Use `MSAC` definitionAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7632 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-22nb/intel/ironlake: Use DMIBAR/EPBAR macrosAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ie0198a44589271de0335a51937e95662db891d98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-22mb/system76/lemp9: convert inverted SCI/SMI macros to _LOW macroMichael Niewöhner
Convert PAD_CFG_GPI_S*I(..., INVERT) to PAD_CFG_GPI_S*I_LOW(...), which is better understandable. Change-Id: I147c82d738623bff54122ad5ef8ece028c562cab Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45488 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22soc/nvidia: Drop unneeded empty linesElyes HAOUAS
Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22soc/cavium: Drop unneeded empty linesElyes HAOUAS
Change-Id: I01227e3c5b650f56e81c5c8e724e3768f06f4530 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44597 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/kontron: Drop unneeded empty linesElyes HAOUAS
Change-Id: Ie106bbc8222dce60c837042a313d069289c79322 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-22acpi: Add SSDT pstate helper functionsJason Glenesk
Add new generic helper functions for PSS, PCT, XPSS, objects. BUG=b:155307433 TEST=Boot Morphius and dump SSDT. Confirm PSS and PCT objects appear as expected and conform to ACPI_6_3_May16.pdf ACPI specification. Check XPSS against Microsoft "Extended PSS ACPI Method Specification" XPSS_spec.doc April 2, 2007. BRANCH=Zork Change-Id: I1ea218bcee33093481e82390550ff96d9d2cb8b5 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-22soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFNSumeet R Pawnikar
Enable processor thermal control using PCI dev path function instead of Device4Enable parameter in devicetree. This change removes the dependency on Device4Enable in devicetree. We can enable and disable this thermal control using on and off support with PCI device entry in devicetree. BRANCH=None BUG=None TEST=Built and tested on dedede board Change-Id: I0463236996ad001af506c9966840b27fe44d60d2 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-22src/mainboard: Add missing <console/console.h>Elyes HAOUAS
"post_code()" needs <console/console.h>. Change-Id: Ice92d5e259b369da949006bf471a0cb249291897 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-22mb/apple/macbook21/acpi: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
It changes the binary for apple/macbook21 because of optimization of "Store" instruction. Generated build/dsdt.dsl files are same. Change-Id: I16b5180f8a8c44e6bc3ef353a99ef92a381b3295 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-22src/lib/bootblock.c: make bootblock_main_with_timestamp publicKangheui Won
bootblock_main_with_timestamp function allows to proceed with existing timestamp table. Apparently we never needed this, but Zork runs verstage in the PSP before bootblock. It'd be useful if we can grab timestamps for verstage from PSP and merge with coreboot timestamps. Making it non-static will enable us to do that. BUG=b:154142138, b:159220781 BRANCH=zork TEST=build firmware for zork Change-Id: I061c3fbb652c40bafa0a007aa75f2a82680f5e0a Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-22soc/amd/picasso: record timestamps in psp_verstageKangheui Won
Verstage in PSP used stub for timestamps since we didn't know about clock. Now we figured out clock source so we can enable timestamp functions. BRANCH=zork BUG=b:154142138, b:159220781 TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-22Revert "soc/intel: Refactor do_global_reset() function"Furquan Shaikh
This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719. Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541 Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-22mb/google/dedede/variants/madoo: Adjust I2Cs CLK to meet specJohn Su
After adjustment on madoo Touch Pad CLK: 381.9 KHz Touch Screen CLK: 389.4 KHz Audio CLK: 380.9 KHz BUG=b:168565823 BRANCH=master TEST=USE=build madoo and measure by scope with madoo. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: If281f9a8614e3e0ef20893b456f46e68ecb0631d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-22superio/ite: Distinguish between chips for PECI readingsMichael Büchler
Some chips can read external temperature sensor values only to TMPIN3. These use EC register 0x55, bit 7 to enable that. This patch adds support for this. It is called "old PECI" by lm_sensors [0]. Other chips can read to any TMPIN[1-3] which is configured in EC register 0x51 like the other temperature sources. This was the only supported method. This patch adds a Kconfig option to indicate this variant. This patch was tested on an Acer Aspire M3800 which has an IT8720F that reads the CPU temperature via PECI. It allows the automatic fan control feature of the Super I/O to work. Overview of support per chip in the coreboot tree, determined from reading the publicly available datasheets or lm_sensors, if noted: Old PECI: * IT8718F * IT8720F * IT8781F, IT8782F, IT8783E/F Normal PECI: * IT8721F (exception: no PECI to TMPIN2) * IT8728F * IT8772E (uses separate code in coreboot, not superio/ite/common) * IT8786E * IT8613E, IT8623E (lm_sensors) [0] Linux kernel 5.4.48, drivers/hwmon/it87.c Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Iab7115852437d46c9b1269bba61ffcf680fe5a6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-21mb/system76/lemp9: gpio: convert the remaining raw pads to macrosMichael Niewöhner
Convert the EC and touchpad interrupt pads from raw to macros. This was done with intelp2m. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I79d2cca0f300e6daf1c1923a1882e4cc1ffc3c8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43648 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/intel/tglrvp: Enable CSE Firmware Lite SKUJamie Ryu
CSE Lite SKU is CSE FW designed for Chrome and this enables CSE Lite SKU support for tglrvp. BUG=None TEST=Build and boot tglrvp with CSE Lite and Consumer SKU Change-Id: Ia5f3e8125b5e7760a62f7fb46aeeae85c32e2037 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41132 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-15 16:41:50 +0000