summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-06-14nb/i945: Drop CHANNEL_XOR_RANDOMIZATION selectionElyes HAOUAS
CHANNEL_XOR_RANDOMIZATION is configurable for no reason. Change-Id: I31e6ed6cb040dcba756cbfd2247d90753d372915 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-14drivers/fsp1_0: select CACHE_MRC_SETTINGS if MRC_CACHE_FMAPMatt DeVillier
Rather than force the user to create the RW_MRC_CACHE FMAP region, simply select CACHE_MRC_SETTINGS so it's done automatically for them. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-14hatch: Fix pen eject wake polarityTim Wawrzynczak
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing devices to wake up on pen insertion instead of removal. Changed to EV_ACT_DEASSERTED. BUG=b:134547896 BRANCH=none TEST=Verified in OS, device only wakes up on pen removal Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14mainboard/google/hatch: Update Helios device treeTim Wawrzynczak
Update Helios device tree override to match schematics. BUG=b:133182138 BRANCH=none TEST=Compiles Change-Id: I3d15fc43651a289d16ffb3cfadaea8f786e858fc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33050 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-14util/superiotool/nuvoton.c: add NCT5539D register dumpPavel Sayekat
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015). Tested on ASUS-H110M-E/M.2 mainboard (Kabylake i3-7100 CPU). Change-Id: Ib55068035ca574b22d0fea81e1a291f7cf0329d3 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-13mb/google/hatch/variants/helios: Use LPDDR3 memoryPaul Fagerburg
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays for mapping SoC DQS pins to LPDDR3 pins. BRANCH=none BUG=b:133455595 TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage` Ensure the firmware builds without error. Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13ec/google/wilco: Read back from EC RAM after S0ix entryDuncan Laurie
We are seeing an EC interrupt after setting the EC RAM offset that indicates that the EC should transition to S0ix mode and this is preventing the kernel from going into S0ix on the first try. As a workaround if we read back from the EC RAM while still in the _DSM handler it seems to prevent this problem. BUG=b:130644677 BRANCH=sarien TEST=ensure s0ix entry works on the first try with sarien Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455 Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13mb/google/sarien: Disable unused GPIOsDuncan Laurie
These 4 GPIOs are being disconnected in the next board so use the board ID to configure these pins as not connected to ensure they do not cause leakage. Also remove the ACPI _PTS S5 code that was configuring the GPIOs. This does mean they will cause small leakage in S5 on existing boards, but it will not affect the new boards. BUG=b:132393441 TEST=boot on sarien with fake board ID and ensure that coreboot configures these pads as expected. Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2019-06-13lint/clang-format: set to 96 chars per linePatrick Georgi
coreboot has decided to go with 96 characters per line. Original Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651 Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-13nb/amd/amdfam10: die() on out of bounds readsJacob Garber
These two functions try to access arrays of lengths 32 and 64 at indices of at most 259 and 71 (respectively). Something here is seriously wrong. This code was introduced in 2007, and aside from cosmetic changes, has had no modifications since then. I don't know what this code is supposed to do, and asking around on IRC, no one else did either. Until someone has the interest and time to work on it, let's at least add a die() to prevent the out of bounds access and alert the user that something is wrong. Change-Id: I5fc15a50a9f0e97add31e3a40da82a15f7427358 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 12296{79-82} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-13Documentation/soc/amd: Add Family 17hMarshall Dawson
Begin a directory for AMD soc devices and add an explanation of how Family 17h works. Newer AMD systems use a unique paradign for initializing the x86 processors. Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Add multilevel PSP directory tableMarshall Dawson
Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Align PSP NVRAMMarshall Dawson
Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13util/amdfwtool: Add argument for soft fuse overrideMarshall Dawson
Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-13util/superiotool: clarify usage of MISC and NANA definesFelix Held
Change-Id: I0b3c5c810bfb05eaec13511391ecd55d7b9eb4e8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13Set ENV_PAYLOAD_LOADER to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enabledSubrata Banik
Change-Id: I416c74ea83ee68370bbeb53834054bcb18e631e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-13stage_cache: Make empty inline function if CONFIG_NO_STAGE_CACHE enableSubrata Banik
This patch removes CONFIG_NO_STAGE_CACHE check from caller function and add empty inline function incase CONFIG_NO_STAGE_CACHE is enable. Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-13mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disableSubrata Banik
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config. Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-13soc/intel/{cml, whl}: Add option to skip HECI disable in SMMSubrata Banik
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13soc/intel/icelake: Replace PCI device LPC to ESPI as per EDSSubrata Banik
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2019-06-13libpayload: Add USB support to mistral configPatrick Georgi
Change-Id: I2ef42f7d607eec6166d762ad71c0d9540906589d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com>
2019-06-12vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12mb/google/octopus: make new targets have DRAM part in CBI by defaultAaron Durbin
All new targets utilizing octopus mainboard support default to always using DRAM_PART_NUM_IN_CBI. This allows easier addition of new targets. BUG=b:132668378 BRANCH=octopus Change-Id: Idb136aa960260abe1657b16ded02a7dfb63c6849 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33370 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12qcom: Add i2c driverPrudhvi Yarlagadda
Add i2c driver in coreboot. Change-Id: I3d39d0325718fc5dd60da42eb2b87dcc4429bfc2 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-12vboot: recovery path should finalize work contextJoel Kitching
Recovery path should finalize work context, and trim vboot_working_data buffer_size. Otherwise, depthcharge ingests the full 12 KB workbuf in recovery path. BUG=chromium:972528, b:134893812 TEST=Build with vboot_reference CL:1584488. Check that USB disks are properly verified in recovery path. BRANCH=none Change-Id: Icf2600d2eb5d846a26aec35a153946dd2f7f128c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-12mb/google/hatch: Disable dynamic clock gating for cr50's GPIOSubrata Banik
Disable dynamic clock gating for the community cr50's IRQ lives on. That IRQ is pulsed very quickly, and with clock gating enabled pulses tend to be missed. This is expecially true on the default 0.0.22 firmware that cr50 comes with out of the factory. BUG=b:130764684 b:130338605 BRANCH=None TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width, observe that even with sub-microsecond pulses no IRQs are missed. Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12Revert "mb/google/poppy/variants/atlas: enable NVMe"caveh jalali
This reverts commit 41979d862a972375d6800afdf2b8b52d408fd220. Reason for revert: NVMe is no longer supported. BUG=b:134752066 Change-Id: I95f2e5f5efe2417700d458f0efd3c793fd8ce8c3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33307 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-11mainboard/google/kahlee: Reduce VRAM to 16MBMartin Roth
It was determined through testing that 16MB of reserved VRAM is sufficient. Additional RAM for the graphics driver is allocated out of system memory. BUG=b:123579702 TEST=Boot Grunt, watch VRAM usage with graphics driver logging. Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-11console: Allow using vprintk() with disabled consoleJacob Garber
The prototype of vprintk() is currently declared unconditionally, which prevents it from being used in situations where the console is disabled. The code will compile correctly, but not link, since the definition in console.c isn't being provided. This adds a shim around the declaration so that, like printk(), a call to vprintk() in this situation will expand to a no-op function instead. Change-Id: Ib4a9aa96a5b9dbb9b937ff45854bf6a407938b37 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-11console: Make die() and friends variadicJacob Garber
die() currently only accepts a fixed message string, which is rather inconvenient when there is extra information that would be helpful to print in the error message. This currently requires an extra call to printk(), which is somewhat awkward: printk(BIOS_EMERG, "Bad table, opcode %d at %d", id, i); die(""); // what do I say here? die() already has a printk() inside it to print the error message, so let's just make it variadic to combine the two. die("Bad table, opcode %d at %d", id, i); // much better Forwarding variadic arguments from one function to another is rather tricky, so die_with_post_code() is redefined as a variadic macro instead. Change-Id: I28b9eac32899a1aa89e086e0d3889b75459581aa Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
2019-06-11Rampayload: Able to build coreboot without ramstageSubrata Banik
This patch removes all possible dependencies in order to build platform with CONFIG_RAMPAYLOAD enable(without ramstage). A. Create coreboot separate stage kconfigs This patch creates seperate stage configs as below 1. HAVE_BOOTBLOCK 2. HAVE_VERSTAGE 3. HAVE_ROMSTAGE 4. HAVE_POSTCAR 5. HAVE_RAMSTAGE B. Also ensures below kconfigs are aligned with correct stage configs 1. COMPRESS_RAMSTAGE and RELOCATABLE_RAMSTAGE are now enable if CONFIG_HAVE_RAMSTAGE is selected. 2. COMPRESS_BOOTBLOCK will enable if CONFIG_HAVE_BOOTBLOCK is set 3. COMPRESS_PRERAM_STAGES will enable if CONFIG_HAVE_VERSTAGE || CONFIG_HAVE_ROMSTAGE is selected. C. Also fix compilation issue with !CONFIG_HAVE_RAMSTAGE On x86 platform: Case 1: ramstage do exist: CONFIG_HAVE_RAMSTAGE=1 >> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_x86_32 Case 2: ramstage doesn't exist: CONFIG_HAVE_RAMSTAGE=0 >> rmodules_$(ARCH-ramstage-y) will evaluate as rmodules_ This patch fixes Case 2 usecase where platform doesn't select CONFIG_HAVE_RAMSTAGE. Also add option to create sipi_vector.manual based on $(TARGET_STAGE) variable. $(TARGET_STAGE)=ramstage if user selects CONFIG_HAVE_RAMSTAGE $(TARGET_STAGE)=postcar if user selects CONFIG_RAMPAYLOAD Change-Id: I0f7e4174619016c5a54c28bedd52699df417a5b7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-06-11soc/amd/common: Add errors for invalid AcpiMmio accessMarshall Dawson
Add a method for the soc/amd/<product> to indicate what AcpiMmio ranges are supported. Induce a build error if soc or mainboard code is added which attempts to use an unsupported block. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=boot grunt, force build errors by removing blocks in iomap.h BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-06-10mb/google/sarien/variants/arcada: Update thermal configuration for DPTFMike Hsieh
Update dptf for arcada DVT2. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Change-Id: I302b7cd4c7e0579acb5482800241b5229cfc49f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-06-10mb/google/poppy/variants/nami: remove redundant breakEric Lai
Break never comes after return, remove it. BUG=N/A BRANCH=firmware-nami-10775.108.B TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I005918d6a04cd21df496dea0f2cb1ed6108675af Reviewed-on: https://review.coreboot.org/c/coreboot/+/33299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10sdm845: qspi: Add Dual SPI supportJulius Werner
This patch adds support for the Dual SPI feature (SDR 2-bit in Qualcomm terminology) to the QSPI controller. Change-Id: I7aed2ccd9627f5de5dd760b418f74d56d2c031d3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33284 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-10spi_flash: Add Dual SPI supportJulius Werner
This patch adds support to read SPI flash in Dual SPI mode, where both MISO and MOSI lines are used for output mode (specifically Fast Read Dual Output (0x3b) where the command is still sent normally, not Fast Read Dual I/O (0xbb) whose additional benefit should be extremely marginal for our use cases but which would be more complicated to implement). This feature needs to be supported by both the flash chip and the controller, so we add a new dual_spi flag (and a new flags field to hold it) to the spi_flash structure and a new optional xfer_dual() function pointer to the spi_ctrlr structure. When both are provided, Dual SPI mode is used automatically, otherwise things work as before. This patch only adds the dual_spi flag exemplary to all Winbond and Gigadevice chips, other vendors need to be added as needed. Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10spi_flash: Make .read() callback optionalJulius Werner
All SPI flash chip drivers currently in coreboot use the generic read functions (spi_flash_cmd_read_fast()/_slow()) as their read callback. The only use case for specialized read callbacks we have left is with specialized flash controllers like Intel fast_spi (which sort of impersonate the flash chip driver by implementing their own probe function). This patch unifies the behavior for all normal flash drivers by making the read callback optional and letting them all fall back to a default read implementation that handles normal fast/slow reading. Most of the drivers used to install the respective callback after checking CONFIG_SPI_FLASH_NO_FAST_READ, but some hardcoded either slow or fast writes. I have found no indications for why this is and spot-checked datasheets for affected vendors to make sure they all support both commands, so I assume this is just some old inaccuracy rather than important differences that need preserving. (Please yell if you disagree.) Also take the opportunity to refactor some of the common spi_flash.c code a bit because I felt there are too many nested functions that don't really do enough on their own, and centralizing stuff a bit should make it easier to follow the code flow. (Some of this is in preparation for the next patch.) Change-Id: I2096a3ce619767b41b1b0c0c2b8e95b2bd90a419 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-06-10spi_flash: gigadevice: Adopt Winbond chip info structureJulius Werner
This patch changes the Gigadevice SPI flash driver to adopt the same structure packing improvements for the hardcoded parameters of individual chips that was implemented for Winbond last year. This cuts the size of the hardcoded info nearly in half and should save us a few hundred bytes in every stage. Change-Id: I9910dcb9b649f51b317f3f8fcba49e5e893f67d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10cbfs_spi: Enable speed logging by default for BIOS_DEBUGJulius Werner
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get in the way (just adding one line per stage, essentially) and should have no notable overhead. Let's enable it by default for the BIOS_DEBUG log level rather than having to recompile to get it. Also fix an issue with building this code on MIPS due to lack of 64-bit division primitives. (This means MIPS and arm32 board may display incorrect results when reading more than 4MB in a single transfer, which sounds very unlikely.) Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10mainboard/hp/z220_sff_workstation: remove unused header fileFelix Held
Change-Id: I4c780afaccd604a1bf4da67eea713f809744ddb2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-09acpigen: Add support for IndexFieldPatrick Rudolph
Add support for generating IndexField, which is similar to Field. Change-Id: If66a627e64953696b0b68488256bd5c141e4c205 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09autoport: Generate a libgfxinit template when IGD is detectedIru Cai
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-09mainboard/Kconfig: add option for a 6144 KB(6 MB) ROM sizeKacper Słomiński
Signed-off-by: Kacper Słomiński <kacper.slominski72@gmail.com> Change-Id: I7a1949c3512528b6b73955d907efc21728eed739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/30980 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09Documentation: Add display panel specificsDaniel Maslowski
Change-Id: If1a393578556d51499c700b68187034830d19215 Signed-off-by: Daniel Maslowski <daniel.maslowski@img.ly> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-09mb/google/hatch: Add 16G 2666 LPDDR3 SPDShelley Chen
One variant is asking for support for 16G 2666 LPDDR3, so adding generic SPD for that. BUG=b:133455595 BRANCH=None TEST=None as this is not being used yet Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-09mb/google/hatch: Add 8G 3200 SPDShelley Chen
One variant is asking for support for 8G 3200 DDR4, so adding generic SPD for that. BUG=b:132920013 BRANCH=None TEST=None as this is not being used yet Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/intel/icelake_rvp: Update FSP-M UPDs to support iclrvp memory initAamir Bohra
Change-Id: Ib55fdfae6e9320c44761682fc134be0731de0fcf Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32522 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09mb/google/dragonegg: Pass FSP-M UPD as per dragonegg requirementSubrata Banik
TEST=Able to boot dragonegg board with LPDDR4 memory. Change-Id: Idbe0aa79879f2b1a754dd1f6718ad4ba1173e760 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31956 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirementAamir Bohra
1. Gfx stolen memory requirement for ICL GFX 2. Enable PeiGraphicsPeim support Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 01:08:55 +0000