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2021-04-10nb/intel/gm45: Use new fixed BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51880 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/gm45/gm45.h: Guard `CxDRC1_NOTPOP` macro parametersAngel Pons
Wrap `r` in parentheses to avoid unexpected behavior with compound expressions. Fortunately, all uses of this macro do not cause issues. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Id0f05a507c5e7e8c50e9765261d86bae73c7b5a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10nb/intel/x4x: Use new fixed BAR accessorsAngel Pons
Some cases break reproducibility if refactored, and are left as-is. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/x4x: Correct and use macros for CLKCFGAngel Pons
The `CLKCFG_UPDATE` macro is copied from gm45 and unused. Correct it and use the CLKCFG macros instead of magic values. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I17e972eba21282ac84c7afe10b7149cd1131fd07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51877 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/x4x/dq_dqs.c: Avoid breaking strings over multiple linesAngel Pons
Breaking strings across multiple lines hurts greppability. Refactor the code a bit to drop one indentation level, and then reflow the strings. Change-Id: I0accdfd0d2c5f58e4da493ba0d4b5c6a067d92c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51876 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/x4x: Add missing newlines to log messageAngel Pons
Change-Id: I67f38bcb1ec0fbbfb7f2f3fcfaf2f9bf2d9ac92c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51875 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/x4x: Reflow long linesAngel Pons
Try to unbreak long lines and user-visible strings. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I1bbf08cf665157840380517302ca581718e3cbe4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/x4x/dq_dqs.c: Fix typo in variable nameAngel Pons
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I143e69446614ddc80562e5931c260329257fd3cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51873 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/x4x: Correct sync DLL phase searchAngel Pons
Bit 4 needs to be set then polled for after changing sync DLL taps. Change-Id: I61b73998dec84710eec0d2561a6f4d88068e3373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51872 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/pineview: Replace remaining BAR accessorsAngel Pons
These changes are not reproducible for some reason. Change-Id: If1fcd0285c3a14686f7deb70d83a4c63d57d62fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51871 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/pineview: Use new fixed BAR accessorsAngel Pons
Some cases break reproducibility if refactored, and are left as-is. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I484f04455fe4baa69888645554fcd72881ba197d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51869 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/ironlake: Use new fixed BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ia0a086bd28b796d2cbe1c7a056922721c95612b8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51868 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel: Replace remaining BAR accessorsAngel Pons
These changes are not reproducible for some reason. Change-Id: I43b445b8af8871db87fb86747db8a35cec75716a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51867 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/sandybridge: Use new fixed BAR accessorsAngel Pons
One instance in northbridge.c breaks reproduciblity when changed. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/haswell: Use new fixed BAR accessorsAngel Pons
There are some cases in `northbridge_topology_init` where condensing the operation using one macro changes the binary, and have been left as-is. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I59c7d1f8d816b95e86d39dcbf7bc7ce8c34f0770 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51865 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/common/fixed_bars.h: Add new read/write accessorsAngel Pons
The {MCH,DMI,EP}BAR macros can be used for both reading and writing. While this can sometimes be useful, compile-time overflow checking is limited. Moreover, and-masks need to be bit-wise negated, which is easy to forget and may result in spurious overflow warnings, and silencing them with a cast also suppresses true integer overflow issues. To address these limitations and for consistency with the existing MMIO API (arch/mmio.h and device/mmio.h), these macros will be replaced with prefixed wrappers around MMIO API functions. However, existing platform code needs to be refactored, and the risk of introducing regressions is substantial. To minimize the risk of breakage, the bulk of the platform code changes will be verified using reproducible builds. This patch introduces the new accessors, to be put to use in follow-ups. These accessors are implemented as macros so that subsequent commits can be verified using reproducible builds. They will be replaced with actual functions after refactoring all platforms. Change-Id: I85376a9e2f6cd042b41036f90de7f9edc7ad4508 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel: Factor out remaining MCHBAR macrosAngel Pons
Except for some formatting differences, the macros are equivalent. Change-Id: I5dc4f115b0873fb96683263ecd152d3d1504647d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51863 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/intel/alderlake: Skip D3Cold for TBTSubrata Banik
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device is in disconnected state. Not adhering this recommendation is blocking the S0ix state transition. BUG=b:183670327 TEST=S0ix state transition occurs with TBT disconnected. Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-10vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v4043Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4043. Previous version was 3444. BUG=b:178846052 BRANCH=none TEST=none Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibada380fe757d9a8b50b2ddfeb2c86b4a98cb5e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-10cbfs: mcache: Fix size calculation for perfectly full cacheJulius Werner
cbfs_mcache_real_size() has a subtle flaw: when the cache is perfectly full to the end (so that the termination token sits exactly at the end of the available space), the loop counting the size ends prematurely. This means that when migrating the cache to CBMEM the terminating token is not copied, which isn't actually noticeable unless you're looking for a file that's not in the cache (because it doesn't exist or because not all files fit when building). This patch fixes the problem and slightly changes the error message for when a cache isn't terminated (to make it more clear that this is a different condition from a "normal" cache overflow that can happen when building if there's not enough room to fit all files). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8d89e7dadc958f97b173b3a2352f2010c8a3d1d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-09MAINTAINERS: Add missing trailing slashFelix Singer
Add missing trailing slash so that Gerrit adds maintainers of xeon_sp as reviewers correctly. Change-Id: Ief6c5d45585a842a1b34a9560c0de37e4b8f03aa Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52211 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/intel/adlrvp: Enable HECI1 communicationSridhar Siricilla
The patch enables HECI1 interface to allow OS applications to communicate with CSE. BUG=None TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0) Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-09mb/google/mancomb: Add Codec configrationEric Lai
Enable I2C2 in devicetree and fill ACPI information for Codec. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add Bluetooth configurationEric Lai
Configure the BT disable GPIO to logic low in order to enable Bluetooth. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Update GPIO configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Enable AP <-> H1 communicationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/mancomb: Add initial I2C configurationEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-09mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDsStanley Wu
Enable Acoustic noise mitigation for boten and set slew rate to 1/8 which is calibrated value for the board. BUG=b:180668001 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-09drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGEArthur Heymans
Rename the Kconfig parameter to more accurately reflect what it does. TPM can be initialised in a different stage too, for instance with VBOOT it is done in verstage. Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-09tests: Add lib/bootmem-test test caseJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic1e539061ee5051d4158712a8a981a475ea7458a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-09include/assert.h: Use mock_assert() for ENV_TEST targetsJakub Czapiga
Some tests have to be able to catch assertion errors. Adding CMocka mock_assert() enables that. Additionally fix test_imd_create_tiered_empty(), test_full_stack() and test_incorrectly_initialized_stack() by adding missing expect_assert_failure(). Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-09drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGEArthur Heymans
This guards code accessing the vboot context which does not exist if vboot starts after romstage. Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-09mb/ocp/deltalake: Override DDR frequency limit via VPD variableTim Chu
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit. Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-04-09mb/{google/jecht,intel/wtm2}: Remove NOOP APM finalize callArthur Heymans
The intel/soc/broadwell smihandler has no handler for this APM call. Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/volteer/var/lindar: Configure unused GPIOs as NCKevin Chang
Configure unused GPIOs as NC BUG=b:180830117 TEST=Build and boot lindar to OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-09payloads/LinuxBoot: make linux kernel build reproducibleAlexander Couzens
Reproducible builds have to be independent from user, host, domain, time. Taken from OpenWrt (GPL2). Change-Id: I420588acc66647051c08e4da6fbedc205cd62877 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35393 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09Makefile: set and export SOURCE_DATE_EPOCHAlexander Couzens
Set SOURCE_DATE_EPOCH [1] to allow payload builds and tools to use this as arbitrary timestamp to allow reprocucible builds. [1] https://reproducible-builds.org/docs/source-date-epoch/ Change-Id: I2c870023d13ff4c95305c8aba1459c1fcaf18773 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-09util/genbuild_h: add COREBOOT_BUILD_EPOCH seconds since epochAlexander Couzens
To use SOURCE_DATE_EPOCH for the kernel build, extend genbuild_h to contain COREBOOT_BUILD_EPOCH. Change-Id: Iaa79d3e7df8101a1ba1b37a361d8992f7eab2d52 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-09Makefile: export LANG LC_ALL TZ without using COREBOOT_EXPORTSAlexander Couzens
LANG LC_ALL TZ are required for reproducible builds. Those environment should be always used for all builds in coreboot and for payloads. By using COREBOOT_EXPORTS those would be removed in payload builds. Change-Id: Iea965abbce23bf6ec408ef587da0a4c4ebc65a27 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-09mb/google/asurada: early-init eMMCWenbin Mei
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. On Hayato Chromebook this can save ~100ms in total. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51973 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09mb/google/asurada: select mmc storage configWenbin Mei
Select mmc storage config for asurada. Build MTK host mmc driver. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-09soc/mediatek: add new driver 'msdc' for eMMCWenbin Mei
Add MTK host mmc driver support. MTK host controller supports eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-08ec/lenovo/h8/acpi: fix wrong calculationMichael Niewöhner
The conversion to ASL 2.0 syntax in commit 81d55cf introduced a regression triggering a BUG in Linux when reading the battery current. Correct the wrongly-converted calculation. Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0") Tested-by: Andrew A. I. <aidron@yandex.ru> Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: Enable postcode on port 0x80Ritul Guru
selecting SOC_AMD_COMMON_BLOCK_USE_ESPI will disable the lpc decodes, so not selecting that keeps the lpc decodes. Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52016 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/amd/bilby: enable boot from NVMe SSDRitul Guru
These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby. Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08soc/amd: remove special GPIO_2 override soc_gpio_hookKyösti Mälkki
This override was added to have the SCI mapping configured if GPIO was used as WAKE_L pin. This however didn't set up the SCI level and trigger information, so it likely never worked as intended. Change-Id: I44661f05c8f517ece88714c625603579731d174b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-08mb/amd,google: use PAD_NF_SCI for GPIO_2 config in soc/amd based boardsFelix Held
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the corresponding SCI mapping register, but didn't set up the SCI level and trigger type, so that couldn't have worked on most of the boards. The only boards where I think this was actually tested are the google/zork ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is GPIO mode instead of the WAKE_L mode, but at least the SCI was configured correctly. The new PAD_NF_SCI macro can configure both the right GPIO mux setting and set up the SCI configuration correctly, so use this new macro for the GPIO_2 pin. For test purposes I also added the corresponding GPIO_2 configuration to amd/mandolin to see if the affected registers end up having the expected value using the HDT debugger to look at the registers, but didn't test the wake-up functionality, since S3 resume isn't working on amd/mandolin yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGSFrans Hendriks
The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig. BUG = N/A TEST = Build and boot facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-08mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMPFrank Wu
Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180. AMDI1015 -> AMD platform with RT1015 10021015 -> AMD platform with RT1015p Reference: https://www.spinics.net/lists/alsa-devel/msg124694.html BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08soc/mediatek: dsi: fine tune the delta time for EoTpJitao Shi
We seperate the EoTp packet extra data. So need to reduce the delta. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 06:13:16 +0000