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2016-12-16mb/intel/kblrvp: Increase preram cbmem console sizeNaresh G Solanki
Some part of preram cbmem console output is truncated. Increase preram cbmem console size to 0xd00 to avoid the same. Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16x86: Configure premem cbmem console sizeNaresh G Solanki
Sometime preram cbmem logs are truncated due to lack of space (default preram cbmem console size is 0xc00). Provide Kconfig option to configure preram cbmem console size so that mainboard can configure it to required value. Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-16Set the fsb timer correctly for Netburst CPUsArthur Heymans
On Netburst (Pentium 4) the fsb cannot be read from MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead. Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17832 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-16drivers/i2c/generic: Allow mainboards to export reset and enable GPIOsFurquan Shaikh
Add power management type config option that allows mainboards to either: 1. Define a power resource that uses the reset and enable gpios to power on and off the device using _ON and _OFF methods, or 2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can directly toggle the GPIOs as required. GPIO type needs to be updated in drivers_i2c_generic_config to use acpi_gpio type so that it can be used for both the above cases. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that elan touchscreen works fine on reef using exported GPIOs. Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17797 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16acpi_device: Add special HID for DT namespaceFurquan Shaikh
BUG=chrome-os-partner:60194 BRANCH=None TEST=Compiles successfully Change-Id: I0fe146cf2235c7c4ad3ea5589ed556884de3a368 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16util/broadcom: Check for successful file accessPatrick Georgi
Change-Id: I5c77b3c5ea3fbc249a8c564a521c2c3c45e1c560 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323510 Reviewed-on: https://review.coreboot.org/17877 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16google/eve: Enable touch devicesDuncan Laurie
Enable the actual touch devices to be probed by the kernel and remove the placeholder devices that I put in before and were used for initial bringup. BUG=chrome-os-partner:58666 TEST=tested on eve Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16tpm2: handle failures more gracefullyVadim Bendebury
When trying to bring up a device with a malfunctioning TPM2 chip, the driver currently gets stuck waiting for SPI flow control, causing bricked devices. This patch puts a 100 ms cap on the waiting time - this should be enough even for a longest NVRAM save operation which could be under way on the TPM device. BRANCH=gru BUG=chrome-os-partner:59807 TEST=with a matching change in depthcharge, now a gru with corrupted SPI TPM comes up to the recovery screen (it was not showing signs of life before this change). Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-16samsung/exynos5420: Fix test for src < 0Patrick Georgi
It was unsigned, not a good place to be for testing < 0. Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1241911 Reviewed-on: https://review.coreboot.org/17888 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-16util/romcc: remove self-assignmentPatrick Georgi
Change-Id: I0f78b55b28011cdefc90665bca2a7ea17647e955 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1129127 Reviewed-on: https://review.coreboot.org/17885 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16util/romcc: Move access after NULL-checkPatrick Georgi
Change-Id: I7f9c38fd6e75b32fe1ed8a60c7054f4dd1fcd5c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1129104 Reviewed-on: https://review.coreboot.org/17884 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/romcc: Fix resource leakPatrick Georgi
Change-Id: I0d260254bab714ec939fc199b3a133b0fc05b10d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1129112 Reviewed-on: https://review.coreboot.org/17883 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/broadcom: Add two more NULL checksPatrick Georgi
Change-Id: I088730fd87dd39fa2c36a06c5770fad05a5808b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323511, #1323512 Reviewed-on: https://review.coreboot.org/17882 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/broadcom: Check return value of stat()Patrick Georgi
Change-Id: Ib53408e8b186c07aa8e42c67131d39c4add05983 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323515 Reviewed-on: https://review.coreboot.org/17881 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/broadcom: Initialize variablePatrick Georgi
It's later tested for NULL, but never initialized to make that test work reliably. Change-Id: Iadee1af224507a6dd39956306f3eafa687895176 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323515 Reviewed-on: https://review.coreboot.org/17880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/broadcom: Close file after usePatrick Georgi
Change-Id: Ieea7ac7fbc618cd12f843f1606f9ebab37cae67e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323508 Reviewed-on: https://review.coreboot.org/17879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/broadcom: Terminate stringPatrick Georgi
filebuffer is treated like a string, so it should be zero-terminated like a string. Change-Id: I078aa39906394be64023424731fe0c7ae2019899 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323473 Reviewed-on: https://review.coreboot.org/17878 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16util/broadcom: close file on errorPatrick Georgi
Change-Id: I5193c6a9f08398b881c971c7175654ba5775b34a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323509 Reviewed-on: https://review.coreboot.org/17876 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16mediatek/mt8173: Check the right set of bits in USB controllerPatrick Georgi
Change-Id: Ic1d1b85a1d7e85b555a93b3a0b55fe310b26e34a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1353362 Reviewed-on: https://review.coreboot.org/17875 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16google/eve: Enable native mode for UART pins in bootblockDuncan Laurie
Put the UART pins into native mode in bootblock so they are not floating when we try to communicate with H1 over I2C. Without a serial console enabled BIOS these pins were not configured until ramstage. BUG=chrome-os-partner:60935 TEST=Boot Eve board without serial console and H1 TPM enabled Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16drivers/i2c/hid: Add generic I2C HID driverDuncan Laurie
Add a generic I2C-HID driver for these types of devices that do not need extra functionality. This allows a new device to be added without having to write a new driver. The i2c-hid PNP0C50 is automatically added as the _CID for the device in the ACPI Device. BUG=chrome-os-partner:58666 TEST=used on eve to describe a new i2c-hid touch controller Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-15mb/roda/rv11: Add new boards Lizard RV11 and RW11Dennis Wassenberg
The Roda Lizard RV11 is a comparatively lightweight, full-rugged notebook. It's based on a 17W TDP dual core Ivy Bridge CPU. The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o options). The RV11 is the first board to use the native graphics initialization by libgfxinit. Tested so far, are the internal eDP port, DP and VGA. Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-153rdparty/libgfxinit: Update to latest masterNico Huber
Changes: o Verification that the framebuffer matches the display mode o Automatic upscaling if the framebuffer resolution is lower than the display mode's o VGA-plane support o HDMI pixel rate is limited to hardware constraints o Error tolerant handling of EDID header-pattern Change-Id: Icbfdf5f37caf99f66847a71f784730aced0826ab Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17775 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-15util/ifdfake: Add number of regionsNico Huber
To make the generated descriptor compatible with latest libflashrom. Change-Id: I005159dd24e72da9cc43119103c96c5dd5b90a55 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17447 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-15mb/ga-945gcm-s2l: Fix resume from suspendArthur Heymans
Checking for memory self refresh can generate false positives, as explained in faa6beb: "northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option". This seems to be the case for this motherboard. TESTED on ga-945gcm-s2l. Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17617 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-15smbios.h: add missing SKU field to type3 tableMatt DeVillier
The type3 SMBIOS table has a non-optional SKU field at the end, which causes a parsing error when missing. Add but do not populate it. Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17851 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15ec/ene932: correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString() where needed Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17783 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-15mainboard/google/reef: clear normal MRC cache on recovery retrainAaron Durbin
For Chrome OS the normal MRC cache should be cleared when a hardware retrain recovery request is observed. The reason is that since there are 2 different MRC cache slots there needs to be a mechanism which allows an end user make a system bootable again if the MRC settings happen to not allow the system to boot any longer. Therefore, one just needs to enter recovery with the hardware retrain flag and the system normal MRC cache slot will be invalidated. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17871 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15soc/intel/common: provide option to invalide MRC cache on recoveryAaron Durbin
Allow a board/platform to invalidate the normal MRC cache when hardware retraining is requested in recovery mode. A small 4 byte payload is used to update the latest data written. It will of course fail on MRC cache retreival on next usage. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17870 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15ec/google/chromeec: query cbmem for retrain statusAaron Durbin
The EC switches, including the hardware retrain flag, are cleared when handing off the vboot state in romstage. However, one may still want to query the state of the hardware retrain flag. Thus, add a method to get the flag from cbmem. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17869 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15lib/cbmem: allow anyone to use cbmem_possibly_online()Aaron Durbin
The cbmem_possibly_online() is a helpful construct. Therefore, push it into cbmem.h so other users can take advantage of it. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17868 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15soc/intel/apollolake: don't probe flash manuallyAaron Durbin
Rely on boot_device_spi_flash() to provide the spi_flash object. There's no need to duplicate the probing logic. BUG=chrome-os-partner:56151 BRANCH=reef Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17867 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15util/cbfstool: Handle error condition more carefullyPatrick Georgi
Change-Id: I72a7776d530d1cf0b8fa39e558990df3dc7f7805 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1295494 Reviewed-on: https://review.coreboot.org/17861 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-15util/cbfstool: check that buffer_create workedPatrick Georgi
We might not care much about this buffer, but we really use it later on... Change-Id: Ia16270f836d05d8b454e77de7b5babeb6bb05d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1294797 Reviewed-on: https://review.coreboot.org/17860 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-15util/cbfstool: Fix memory leakPatrick Georgi
Change-Id: I66cb1c88155ef58610bacfb899e0132e4143c7ac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1325836 Reviewed-on: https://review.coreboot.org/17859 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15util/cbfstool: Add NULL-ptr checkPatrick Georgi
Change-Id: I8b5caf5423135fe683a24db6700b895a2685cb98 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1323507 Reviewed-on: https://review.coreboot.org/17858 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15google/reef: Remove VARIANT_DIR definitionMartin Roth
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be defined in each mainboard. Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17841 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15drivers/i2c: Pass in i2c_generic_config into i2c_generic_fill_ssdtFurquan Shaikh
Remove any assumptions required for the drivers using i2c_generic to have drivers_i2c_generic_config structure at the start of the driver config. Instead pass in a pointer to drivers_i2c_generic_config from the calling driver. Change-Id: I51dc4cad1c1f246b51891abf7115a7120e87b098 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17857 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-15ec/chromeec: Correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString(). Change-Id: I4fdbf97e9b75030374dffc99a954dd9faa6a5209 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15pcf8523: Fix wrong initialization of several registersWerner Zeh
In the case where the RTC is initialized after the battery is completely drained the bits for power_mode and cof_selection are set up with wrongly applied masks. In the case where the RTC is re-initialized again with no power-loss after the last initialization the bits for cap_sel, power_mode and cof_selection are not shifted to the right position. Both errors lead to a wrong initialization of the RTC and in turn to a way larger current consumption (instead of 120 nA the RTC current rises to over 2 µA). This patch fixes both errors and the current consumption is in the right range again. TEST=booted mc_bdx1 and verified current consumption of RTC Change-Id: I8594f6ac121a175844393952db2169dbc5cbd2b2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17829 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15util/abuild: Fix update_config functionMartin Roth
- Because $configoptions contains embedded newlines that we want to be interpreted when we pipe it out to the config file, change that back to a printf, and tell shellcheck that we want to do it. - 'make olddefconfig' & 'yes "" | make oldconfig' give us the same output for the config file, but olddefconfig doesn't generate the log the way oldconfig does. Go back to the previous behavior. - Don't overwrite the config log with make savedefconfig. Change-Id: I4966a3bb2541b452eeb4ca73ac3cd727f8525636 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17853 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-12-153rdparty/blobs: Update for AMD Stoney RidgeMarshall Dawson
Update the blobs submodule to bring in the binaries for 00670F00. This also corrects some formatting in the various license.txt files. Change-Id: I7a70d1168734d06ef6919d83dd73bc8f2bc4173c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17872 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins)
2016-12-14lib/spd_bin: Check return code & remove dead codeNaresh G Solanki
Remove dead code to address CID 1366756 Control flow issues (DEADCODE) Add return value check to address CID 1366755 Error handling issues (CHECKED_RETURN) Found-by: Coverity Scan #1366755 Found-by: Coverity Scan #1366756 Change-Id: Id02f6915ec7c6a4abfce20332c55833683e52d77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17838 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-14libpayload/drivers/video: Improve check in if conditionPatrick Georgi
Coverity considers this a copy&paste error, and maybe it is. In any case, it makes sense to check the variable that (if the condition is true) is changed, and the values are the same before that test, so the change is harmless. Change-Id: I163c6a9f5baa05e715861dc19643b19a9c79c883 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347376 Reviewed-on: https://review.coreboot.org/17837 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14libpayload/.../PDCurses: Improve compatibility with ncursesPatrick Georgi
Coverity erroneously complains that we call wmove with x or y == -1, even though our copy of that function properly checks for that. But: setsyx is documented to always return OK (even on errors), so let it do that. (and make coverity happy in the process) Change-Id: I1bc9ba2a075037f0e1a855b67a93883978564887 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1260797 Reviewed-on: https://review.coreboot.org/17836 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14vendorcode/amd: drop dead codePatrick Georgi
Change-Id: Ie67e1f7887e8df497d7dfd956badd9e06fd5d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1254651 Reviewed-on: https://review.coreboot.org/17833 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-14libpayload/.../PDCurses: avoid reading orig before NULL checking itPatrick Georgi
Coverity complains and that (unfortunately) means that some compiler might take advantage of the same fact. Change-Id: I59aff77820c524fa5a0fcb251c1268da475101fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1261105 Reviewed-on: https://review.coreboot.org/17835 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14vendorcode/amd: Fix non-terminating loopPatrick Georgi
Code is copied from agesa/common's amdlib.c. Things can probably be deduplicated. Change-Id: I9c8adab5db7e9fd41aecc522136dfa705c1e2ee6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229662 Reviewed-on: https://review.coreboot.org/17834 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2016-12-14soc/intel/broadwell/lpc.c: don't zeroize existing gnvs tableMatt DeVillier
The gnvs table only needs to be zeroized after init; zeroizing an existing/populated table renders all I2C devices completely non-functional. TEST: boot Linux and observe all I2C devices functional Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17828 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 21:16:23 +0000