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2015-11-16Revert "Drop SuperIO nuvoton/nct6779d"Stefan Reinauer
This reverts commit 42444f6f53d47604d9a44c9e109b5717efaed74f. Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f Reviewed-on: http://review.coreboot.org/12328 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp_baytrail: Load APs microcode in baytrail_init_cpusYork Yang
Load microcode to APs when performing baytrail_init_cpus. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/12095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp_baytrail: Load BSP microcode in bootblockYork Yang
Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found. Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp1_0: Use dummy microcode when calling FSP TempRamInitYork Yang
Pass in dummy microcode when calling FSP TempRamInit API. FSP will not do the microcode load and leave the work to coreboot. Ensure that BSP has been loaded a microcode before calling TempRamInit API, otherwise FSP will return error that No Valid Microcode Was Found. Change has been verified on fsp_baytrail and will be applied to rangeley. Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11895 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
Load microcode to APs when performing model_406dx_init. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
Load microcode to BSP in bootblock so later on the FSP TempRamInit call will return with success. The updated fsp1_0 driver calls TempRamInit API with dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded with microcode before calling TempRamInit API, the call will fail with error No Valid Microcode Was Found. Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-16nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slotsTimothy Pearson
The current code did not define the number of DIMM slots on the mainboard, which lead to incorrect configuration values and occassional training failure. Add preliminary support for DIMM slot count configuration. Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16cpu/amd/fam10h-15h: Fix BSP stack corruption on 32-core Fam10 systemsTimothy Pearson
On some multi-socket AMD platforms there are too many cores for all APs to start up without stack collisions with either each other or the BSP. On such platforms a larger amount of CAR memory is also available. Allow the maximum DCACHE size to be increased via a mainboard- specific Kconfig flag. Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12015 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-15amd/model_fxx: Check FID&VID Support for the BSP (too)Urja Rannikko
Tested: Avoids crash with Sempron 2800+ on K8V-X. Change-Id: I76196176635bb0f6ac284c8cb3b72212774fdfe4 Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-on: http://review.coreboot.org/12336 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-11-15northbridge/amd/amdmct: Reduce maximum number of DDR3 DIMMsTimothy Pearson
CAR space on certain platforms is nearly full. This prevents the addition of necessary RAM initialization features such as x4 DIMM support. As the DIMM SPD cache uses a sizeable amount of CAR RAM, reducing it would free up a significant amount of CAR RAM. DDR3-based AMD platforms only support up to 3 physical DIMMs on each channel (6 per node). Reduce the maximum number of DIMMs on a node from 8 to 6 accordingly. Change-Id: I38def86da76fc622785318c825670209b2ac9017 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12107 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-15src/southbridge/amd/sr5650: Always configure lane director on startupTimothy Pearson
On the ASUS KGPE-D16 it was noted that the pin straps did not properly configure the lane director hardware, causing link training failure on NIC B. Forcing coreboot to always reconfigure the lane director on startup resolves this problem. Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12014 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failureTimothy Pearson
In the course of adding full Family 15h MCT support some Family 15h specific settings were inadvertently applied to Family 10h processors. Only apply Family15h specific settings to Family 15h processors. Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12013 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registersTimothy Pearson
Change-Id: Icb2754143762bd64ee1df5674fa071de1c595eaf Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12012 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in useTimothy Pearson
When both DCTs of a node are in use the DRAM clocks should be skewed with respect to one another in order to reduce cross-channel interference. Set the clock skew bit according to the BKDG recommendations. Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12011 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt valuesTimothy Pearson
The existing code did not set Rtt timing parameters when registered DIMMs were used with Family 15h processors. Set the Rtt values according to the BKDG recommendations. Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12010 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangsTimothy Pearson
Change-Id: Iaf826b6a0c8e929372519f6d97933515a80f0b39 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12009 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issueTimothy Pearson
AMD Opteron processors contain a very fragile phy phase detection circuit. Additionally, the algorithm given in the BKDG does not function as intended; this was verified both on real hardware via execution trace and on paper with values read back from multiple CPUs and DIMMs. As a result, the phy training algorithm given in the BKDG has been replaced with a phy training algorithm developed at Raptor Engineering. This particular patch is the first part of that algorithm; the code is updated in future patches but this should exist in the historical record in case something breaks down in the later sections of code. Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12007 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errorsTimothy Pearson
AMD's automatic phy phase detection hardware is very fragile and often produces incorrect results. Attempt to recover from obvious phase locking errors by retrying phy training on the failing link. Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT valuesTimothy Pearson
The existing MCT code did not properly set up the On Die Termination (ODT) or timing values for registered DIMMs. Use the BKDG recommended values when registered DIMMs are installed. Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12005 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15cpu/amd: Fix AMD Family 15h ECC initialization reliability issuesTimothy Pearson
There were numerous issues surrounding AMD ECC initialization on Family 15h processors due to the incomplete derivation from Family 10h MCT code. Bring the Family 15h ECC initialization and supporting setup code in line with the BKDG recommendations. Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12003 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC initTimothy Pearson
The existing ECC initialization algorithm contained several bugs on both Family 10h and Family 15h processors, including activation of ECC scrub before DRAM setup was completed, in violation of both BKDG and errata recommendations. Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12002 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15southbridge/amd/sb700: Fix random persistent SATA AHCI drive detection failureTimothy Pearson
Change-Id: I4202a62217a7aaeaba07e4b994a350e83e064c9c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-14northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statementsTimothy Pearson
Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12008 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-14cpu/x86/lapic: Add stack overrun detectionTimothy Pearson
Change-Id: I03e43f38e0d2e51141208ebb169ad8deba77ab78 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-14northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tablesTimothy Pearson
Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-14sconfig: remove warning about root_complexPatrick Georgi
It's not deprecated if it's still in active use. The code layout is just "funny" (and could warrant a chipset-side cleanup, but not today) Change-Id: I5f7776ceba0134f20364a0c4a1ca51382e9877e2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12429 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-13newisys: Remove mainboard directory and Kconfig filesMartin Roth
Since there are no longer any newisys mainboards, remove the directory and Kconfig files. This removes the Kconfig warning: mainboard/newisys/Kconfig:3:warning: config symbol defined without type Change-Id: Icb2e782173166a26fa261f6cfb81b665a846931e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12423 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13cbfstool: Allows mixed-state fmap regions to workPatrick Georgi
When using FMAP regions (with option -r) that were generated with a master header (as done by cbfstool copy, eg. in Chrome OS' build system), there were differences in interpretation of the master header's fields. Normalize for that by not sanity-checking the master header's size field (there are enough other tests) and by dealing with region offsets properly. BUG=chromium:445938 BRANCH=tot TEST=`cbfstool /build/veyron_minnie/firmware/image.dev.bin print -r FW_MAIN_A` shows that region's directory (instead of claiming that there's no CBFS at all, or showing an empty directory). Change-Id: Ia840c823739d4ca144a7f861573d6d1b4113d799 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e5364d291f45e4705e83c0331e128e35ab226d3 Original-Change-Id: Ie28edbf55ec56b7c78160000290ef3c57fda0f0e Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312210 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12416 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13cbfstool: Add way to access entire backing data for a bufferPatrick Georgi
This is required to handle certain relative-to-flash-start offsets. BUG=none BRANCH=tot TEST=none Change-Id: I8b30c7b532e330af5db4b8ed65b21774c6cbbd25 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 596ba1aaa62aedb2b214ca55444e3068b9cb1044 Original-Change-Id: Idc9a5279f16951befec4d84aab35117988f7edb7 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312220 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12415 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13intel/kunimitsu: This patch enables wakeup from S0ix using headset button.Saurabh Satija
Kernel needs to set Audio IRQ as wake capable. BUG=chrome-os-partner:47450 BRANCH=NONE TEST=System wakes up from S0ix by pressing headset buttons. Change-Id: I0f89d05b4c5449e5e3277dde938d941e4ad8cbea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65bf434f7c7e1662211f9c8bf61eeb4f41bdc675 Original-Change-Id: I7b5b564023044b4458eb0976488018b3226f4c70 Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12414 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13libpayload: udc/dwc2: Ignore setup packet in check for queue emptyFurquan Shaikh
during shutdown DWC2 UDC controller always requires an active packet to be present in EP0-OUT to ensure proper operation of control plane. Thus, during shutdown ignore EP0-OUT for queue empty check if only 1 packet is present. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. "fastboot reboot-bootloader" reboots device without timeout in udc shutdown. Change-Id: Iafe46c80f58c4cd57f8d58f060d805b603506bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4e7c27d849c0411aae58e60a24d8170a27ab8485 Original-Change-Id: Ifa493ce0e41964ee7ca8bb3a1f4bb8726fa11173 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311257 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12413 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-11-13libpayload: queue: Add a helper macro for checking singleton queueFurquan Shaikh
Check if the simple queue consists of only 1 element. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. Change-Id: Ib257a5e6b9042b42c549f8ad8b943e3b75fd8c9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5435d6fec1c4fbb4c04ba5b8c15caff9ee4e50f0 Original-Change-Id: I7a8cb9c4e7e71956e85e65b3e7b8e0af4d354110 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311256 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12412 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-11-13intel/skylake: ensure the RTC time is setAaron Durbin
In 2014 or so the RTC code was changed to assume the ALTCENTRY register (0x32) as always being utilized for creating an rtc_time. However, one needs to ensure it's set at least once otherwise the year field in rtc_time is not sane. In practice this doesn't matter unless somone wants to use the full year value. cmos_init() should do the same thing in the rtc fail case, but the machine I had never had that set correctly. BUG=chrome-os-partner:47388 BRANCH=None TEST=Booted glados w/ 0xff ALTCENTRY value. New value is 0x20. Change-Id: I028f801c5d717a0018ed00df82c25b466d64670c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d5be5bc697bef60a264ddc7f67755aa96088d36 Original-Change-Id: I6e12a30c9e08d8c1002e4cef0f143f0f88009e92 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311264 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12411 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13elog: fix improper assumption for year valuesAaron Durbin
The elog format stores the year of the event in bcd format. Semi-recently rtc_get() started returning the full year, e.g. 2015. However, bin2bcd takes a uint8_t as a parameter. Converting a full year (2015 or 0x7df) to a uint8_t results in passing bad values (223 or 0xdf) to bin2bcd. In other words the input value of bin2bcd needs to be a number between 0 and 99. Therefore fix that mistake. BUG=chrome-os-partner:47388 BRANCH=None TEST=Events show up with correct year in eventlog now. Change-Id: I9209cb9175c0b4925337e2e5d4fea8316b30022a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 95a86013234dc999c988291f636e2db3803cc24a Original-Change-Id: I12734bc3a423ba9d739658b8edc402b8d445f22e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311263 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12410 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1zbao
1. This is required the BLOB change Ie86bb0cf AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5) 2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12southbridge/amd/sb700: Fix SATA port 4/5 drive detectionTimothy Pearson
Change-Id: I01481f25189d01b6f4ed778902b2ecc4d39c7912 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12southbridge/amd/sb700: Recover if AHCI disk detection failsTimothy Pearson
The SB700 silicon is somewhat buggy; if the links come up in an incorrect state after POR the silicon cannot automatically recover. If a disk fails to come online, reset the associated link and try disk detection again. Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12northbridge/amd/amdmct/mct_ddr3: Update prefetcher configurationTimothy Pearson
The existing prefetcher configuration was incorrect; use the correct values from the AMD Family 10h and Family 15h BKDGs as appropriate. Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12417 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12northbridge/amd/amdmct: Clear memory before enabling ECCTimothy Pearson
The existing code enabled ECC before clearing memory. As the AMD CPUs will generate MCEs on any invalid check bits, this resulted in random lockups during memory training due to the uniniailized check bits. Initialize ECC check bits before enabling ECC hardware. Change-Id: I992e7040520570893ba6a213138dd57bfa14733b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startupTimothy Pearson
In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts), with the probability of a failure increasing with the number of disks connected to the controller. Resetting the SATA controller appears to show the true state of the underlying hardware, allowing the drive detection code to attempt link renegotiation as needed. Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11998 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-12southbridge/amd/sb700: Do drive detection even in AHCI modeTimothy Pearson
SeaBIOS AHCI drive detection randomly fails for drives present on the secondary channel of each AHCI SATA BAR. Forcing native drive detection in AHCI mode resolves this issue. Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12mainboard/asus/kgpe-d16: Add sata_alpm CMOS optionTimothy Pearson
Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS optionTimothy Pearson
Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12408 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12src/northbridge/amd/amdmct: Add option to override bad SPD checksumTimothy Pearson
Certain DIMMs, for example DIMMs on which the EEPROM has been modified by the end user, may not contain a valid SPD checksum. While this is not a normal condition, it may be useful to allow a checksum override while memory timing parameters are being altered, e.g. in the course of overclocking or underclocking, or when recovering from a bad SPD write. This is an advanced level feature primarily useful for debugging and development. Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11987 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-12AMD/Mullins: Fix the interrupt routingZheng Bao
The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. run 'cat /proc/interrupts' to see if devices actually use no-msi. Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12363 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12AMD/Kabini: Fix the interrupt routingZheng Bao
The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. run 'cat /proc/interrupts' to see if the devices actually use no-msi. Change-Id: Id6d35224312aeb6e3a175ec9990e0bb34bad67e7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12362 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12southbridge/amd/sb700: Add option to disable SATA ALPMTimothy Pearson
The AMD Register Programming Reference states that the user should have the option to disable Active Link Power Management for two reasons. First, some drives may not function correctly with the ALPM implementation of the SP5100, and second there are some situations where low latency access is more important than the power savings created by using ALPM. Allow the user to disable ALPM if desired. Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE cardTimothy Pearson
Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11988 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12northbridge/amd/amdmct: Verify MCT NVRAM options before skipping trainingTimothy Pearson
Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS optionTimothy Pearson
Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12407 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
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