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2018-10-04libpayload/x86/exception: Add ability to ignore unknown interruptsRaul E Rangel
This will make enabling the APIC safer by ignoring unknown interrupts and not halting the system. Once all interrupt sources have been found and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired. BUG=b:116777191 TEST=Booted grunt, halted the kernel, and pushed the power button while in S5. Verified that depthcharge logged the unknown exception. APIC Init Started APIC Configured Ignoring interrupt vector 39 Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/x86/exception.c: Remove exception_install_hookRaul E Rangel
Not used by x86 code anymore. BUG=b:116777191 TEST=Validated that depthcharge can be built. Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/apic: Register a spurious interrupt vectorRaul E Rangel
We should have a spurious interrupt vector just incase we get one. The handler doesn't need to do anything. BUG=b:116777191 TEST=Booted depthcharge on grunt and inspected the register. I can't generate a spurious interrupt, so I can't validate that the handler gets called. Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04libpayload/apic: Only ACK interrupts triggered by the APICRaul E Rangel
Only set end of interrupt (EOI) when the APIC In-Service vector matches the interrupt vector. This makes it so we don't EOI a non APIC interrupt. BUG=b:116777191 TEST=Booted grunt with APIC enabled and verified depthcharge still works. Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04console: Enable CONSOLE_USB by defaultNico Huber
It seems to be the only user of the USB debug driver. So having to enable it separately seems wrong. It still depends on the selection of the EHCI debug driver. Change-Id: I5f5f38a912423d9b8f1e71ae875b6a14fdee651c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-10-04mb/intel/cannonlake_rvp: Move FSP param override function to separate fileRizwan Qureshi
Move the FSP param initialization function to a separate file, as being done on the SoC side and remove the empty romstage.c file. Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04soc/intel/cannonlake: Move the FSP related callbacks to separate filesRizwan Qureshi
Move funtions callbacks used to override FSP upd values to separate files. This serves as a base change for SoCs for which FSP is still under development, and hence the FSP header files are not available yet and in turn the UPDs cannot be referred. These newer SoCs will implement empty callbacks. The code will compile with basic header files which only include the architectural FSP structures. This allows plugging in these separate files for compilation in an environment where FSP header files are available. The fact is, FSP header files are not released externally until PRQ. However the teams at intel and some partners have access to the development version of these files. This code refactor helps to continue development on the pre-PRQ silicons and submit related code to coreboot.org. BUG=None BRANCH=None TEST=Build for cnlrvp Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04arch/x86: Make mb/romstage.c optionalRizwan Qureshi
Currently src/mainboard/*/romstage.c is mandatory for compiling, this makes having the file present even though there is nothing to initialize in romstage on the mainboard side. Eliminate the need to have empty romstage.c files using the wildcard function. BUG=None BRANCH=None TEST= build cannonlake_rvp after removing the romstage.c file. Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-04soc/nvidia/tegra124: Increase bootblock sizePatrick Rudolph
Increase bootblock size by 4KiB and reduce romstage by 4 KiB. Change-Id: I604fd9c63a4cf6fb7b18249a6d73cd637e184a71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04mb/google/poppy/variant/nocturne: update GPIO configurationNick Vaccaro
GPP_C19 is not being set as the code is incorrectly setting GPP_C16 instead, causing SAR sensor not to work, so this change sets GPP_C19 to NF1. GPP_E3 is not being initialized in the code. Initialize GPP_E3 to a no connect as documented in the board schematic. BUG=b:117124878 TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and verify that i2c transactions work for the left SAR sensor. Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28867 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variant/nocturne: increase touchscreen reset delayNick Vaccaro
Increase the reset delay for the touchscreen to 10 ms. BUG=b:116857433 TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, log in and execute the following two commands: echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind and verify the bind command does not echo back a "-bash: echo: write error: No such device" error. Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28803 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04soc/intel/common: add acpi_get_sleep_type to pmclibBora Guvendik
Change-Id: I3f4123657a375211f802a7d484a15353f9a256e9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-10-04amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 statusEdward Hill
Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers on boot. print_num_status_bits() was already using BIOS_DEBUG. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28885 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04amd/stoneyridge: Prepare for vboot rebooting systemMarshall Dawson
Implement the function vboot_platform_prepare_reboot() which is normally a weak function. The SlpTyp field of the PM1 register is not reset to its default value when the APU restarts. This change prevents a failing condition if vboot decides to reset the system instead of allowing an S3 resume to continue. TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead BUG=b:117089826 Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28877 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variants/rammus: Shorten oem_table_id to RAMMUSmarxwang
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS" so that the audio topology file can be loaded properly by the operating system. BUG=b:112945714 BRANCH=master TEST=There is no error message like "failed to load topology firmware" in kernel v4.4 log. Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addressElyes HAOUAS
Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28847 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04Documentation/.../gerrit_guidelines: Remove trailing colon from headingsJonathan Neuschäfer
They are unnecessary in headings, and look slightly irritating in the table of contents. Change-Id: I7344026f5753aebdd73f9fe414e96730c823ac26 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-04sb/amd/pi/hudson: Remove #if 1Jonathan Neuschäfer
Change-Id: I4cf69dc3df2afaa8f33864374ea93548ab7ad810 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04Documentation: Spell "blob" in lowercaseJonathan Neuschäfer
It's not an acronym (outside of database software). Change-Id: I529561e4fc9889be7f9d6bd6d5f9a876e2007671 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04util/abuild/abuild.1: Fix references to CBROOT parameterJonathan Neuschäfer
One occurence of this parameter was changed from LBROOT to CBROOT in f8ee1806ac ("Rename almost all occurences of LinuxBIOS to coreboot."). Change the others, too. Change-Id: Ic0da24c32cd6d2f0577de037b5463c800f455786 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04MAINTAINERS: Update RISC-V entry with SiFive and utilsJonathan Neuschäfer
Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
Clang doesn't understand -march=riscv64imac and -mcmodel=medany, so don't use them when running the clang static analyzer. On the other hand, __riscv and __riscv_xlen need to be defined in order to select some macros in src/arch/riscv/include/arch/encoding.h. __riscv_flen selects the floating-point paths in src/arch/riscv/misaligned.c. -mabi is moved with -march for consistency. A complete list of preprocessor definitions on RISC-V can be found at https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions With this commit, scan-build produces a useful result on RISC-V. Change-Id: Ia2eb8c3c2f7eb5ddd47db24b8e5fcd6eaf6c5589 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04cpu/intel/car: Fix typoElyes HAOUAS
Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-04mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for FleexIvy Jian
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT. BUG=b:116721822 TEST=Verified it in Fleex EVT board which rework ram id. Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQDuncan Laurie
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04ec/google/chromeec: Define a sync IRQ if neededDuncan Laurie
Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-10-03mb/google/kahlee: Update careena Audio/TP i2c timingKevin Chiu
After adjustment on Careena Audio: 402.805 kHz -> 396.8 kHz TP: 406.1 kHz -> 399.5 kHz BUG=b:110984023 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ia3eb91ca3772d5f122498e3989ec03838fce06a5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03google/kahlee: Enable IOMMU deviceMarc Jones
Enable the IOMMU device on all kahlee based mainboards. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28754 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-03soc/amd/stoneyridge: Add IOMMU supportMarc Jones
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03Documentation/mb/lenovo/t4xx_series: Change "Steps to access the flash IC" ↵Jonathan Neuschäfer
to sub-heading This heading should not be a top-level heading, because it's not at the top of the file. Also remove the trailing colon, because it's unnecessary in a heading. Change-Id: I0685bb8734ad899c29618d24c0497e4fb8c0d01c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-03soc/intel/commom/block/i2c: Make I2C controller out of resetSubrata Banik
This patch ensures I2C controllers are out of reset without any assumptions. BUG=b:116191230 BRANCH=none TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT at reset (by reading Bit 0-1 as 3) Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-02src/soc/intel/broadwell/me.c: Correct HMRFPO misspellingAngel Pons
`HMRFPO` was spelled as `HMRPFO` twice. Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-02soc/intel/skylake: Fix spelling mistakeSubrata Banik
Make correct spelling for THERMAL_IRQ macro in irq.h file. Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-02soc/intel/skylake: Replace white space with tabSubrata Banik
This patch unified line indentation. Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-01drivers/intel/wifi: Add DID for Intel WIFI module 8260, 8275Subrata Banik
Change-Id: I38d83370e96cff6822a96da5fa3d9af797ba1dc1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-01libpayload/drivers/usb: Fix leaksPatrick Rudolph
Don't leak buffers on device detach. Tested on qemu using: qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \ -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \ -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd Change-Id: Ib2d80dd4590aa0dacdf2da3b614c6505c931d0be Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01libpayload/drivers/usb: Fix broken retry counterPatrick Rudolph
Exit on first sucessful CONTROL transfer instead of doing GET_DESCRIPTOR_TRIES iterations. Tested on qemu using: qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \ -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \ -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd Change-Id: I7c881c08d94636a43223338e46c876b5f3e27d47 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01mb/google/octopus: Operate touchpad I2C CLK in specChris Zhou
Need to tune I2C bus 6 clock frequency under the 400K Hz Bug=b:115600671 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 398.07K Hz Change-Id: I5cc1f67f0db0553cb8424f81408ed4686cddb2fb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-01src/Kconfig: Drop a superfluous wordJonathan Neuschäfer
Change-Id: I2d658e57d52f79c77be08599b9e525a46e30f732 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01google/kahlee: Run FCH PTS and WAK methodsMarshall Dawson
The FCH ASL is now capable of controlling the D-states of most AOAC devices, as well as properly reinitializing the xHCI firmware on a resume. Call the FPTS and FWAK methods. BUG=b:77602074 TEST=On Grunt, go to S3 and wake with a USB keyboard Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28773 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB ASL for D0/D3coldMarshall Dawson
Add methods, and call them, for transitioning EHCI and xHCI to D0 or D3cold. Add device objects necessary for waking the system via USB. In order for USB to wake the system, it must be in the D3cold state. Then on resume, its firmware must be reloaded. This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI package), and has been modified to fit the coreboot ASL names. In addition, AMD's methodology is to generate a SW SMI for saving/restoring certain settings. This has been ported into U3D0 and U3D3, as the necessary registers are now publicly documented. BUG=b:77602074 Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28772 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL helper for AOAC PwrGood ControlMarshall Dawson
Add a method to assist with setting the PwrGood Control register, which will be useful for various devices. BUG=b:77602074 Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Add FCH WAK and PTS methodsMarshall Dawson
Add methods that can be used for preparing all controller hub devices for sleep, and that will turn the devices back on. BUG=b:77602074 Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28770 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL for D-states on AOAC devicesMarshall Dawson
Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package) that can put AOAC devices into D0 or D3cold. The argument numbers coincide with the AOAC register offsets for the various devices. SATA, USB, and SD require additional device configuration. Add a placeholder and mark as todo. BUG=b:77602074 Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28769 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASLMarshall Dawson
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define various PCI config space registers. These are duplicated from AMD's FchCarrizo.asl file. BUG=b:77602074 Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28768 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Load AOAC and USB gnvs valuesMarshall Dawson
Indicate the devices that are enabled. This is somewhat rudimentary, but could be improved in a later patch (e.g. get settings from devicetree). Calculate values that may be used for reinitializing the xHCI firmware. Add the EHCI BAR's current base address to gnvs. BUG=b:77602074 Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28767 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB settings to gnvsMarshall Dawson
A later patch will rely on two USB settings from the BIOS. Add these to the global_gnvs_t structure. The first is a data that will be used to locate the xHCI firmware for reloading after a resume. Although the existing calculations will be somewhat simple, keeping this on the coreboot side will help in the event multiple FWs are eventually in the build. The second item is a usable EHCI base address that may be programmed during S3 suspend and resume. At the time the PTS and WAK code runs, the BAR will be clear. BUG=b:77602074 Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Create gnvs entries for AOAC devicesMarshall Dawson
A later patch will leverage AMD's ASL support for handling AOAC devices. This will gather coreboot's device enables from a bitwise field, where each bit corresponds to the register offset used to control each devices. Create an identical structure, and add it to the nvs ASL and global_nvs_t structure. BUG=b:77602074 Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-01drivers/spi/winbond: Fix read protection bitsPatrick Rudolph
Don't care about SRPx and print correct protected range. Change-Id: I051f1459c585a7ed6a4878dc217d11df5ef00d74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 22:40:00 +0000