summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-11-22vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFSFurquan Shaikh
If AGESA is added as a raw binary (and not a stage), then cbfstool does not perform relocation. In this case, it should be added only to COREBOOT (i.e. default) CBFS since the binary needs to be present only in one specific location that is present in the default CBFS. Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22util/inteltool/ivy_memory.c: Do not rely on MR0 valuesAngel Pons
MR0 may not always be programmed in the training result registers. Thus, do not rely on its values. Also account for per-channel differences. Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-22util/inteltool/ivy_memory.c: Properly mask tAONPDAngel Pons
This field is only 4 bits wide. Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons
This register needs to be updated differently depending on the CPU generation and stepping. Handle this as per reference code. Further, introduce a bitfield for the register to make the code easier to read. Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons
Values differ between Sandy and Ivy Bridge. Remove the lookup table, since it contains duplicated values and is hard to see which values correspond to which frequencies. New values come from reference code. Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons
This is actually aggressive write training, similar to aggressive read training. Rename it accordingly and refactor it to improve clarity. Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done for later Ivy Bridge steppings. Therefore, guard the code accordingly. Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Only use write Vref if supportedAngel Pons
Only some Ivy Bridge SKUs support write Vref control. Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Lower tPRPDEN to 1Angel Pons
This is the default value, and matches what vendor firmware does. Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Increase tRWDRDD with fast RAMAngel Pons
This has been reported to increase stability, and vendor BIOS also does the same. Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
This is actually an (incomplete) aggressive read training algorithm. Rename functions and variables accordingly, and tidy up declarations. Tested on Asus P8H61-M PRO, still boots. Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Relocate PREA-ACT-RD sequenceAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Remove spurious writes to IOSAV BW maskAngel Pons
The byte-wise error mask only needs to be set for certain corner cases in read MPR training. Thus, minimize writes to this register. Tested on Asus P8H61-M PRO, still boots. Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Drop `precharge` functionAngel Pons
This is a copy of `find_predefined_pattern` without any effect. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded valueFelix Singer
Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-22nb/intel/sandybridge: Clarify register writeAngel Pons
It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Encapsulate JEDEC write levelingAngel Pons
Create and rename a few functions to contain the entire JEDEC write leveling algorithm. Not all write training is JEDEC write leveling. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie9c6315340164029e30354723b4103d906633602 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Do not rewrite write leveling sequenceAngel Pons
There's no need to reprogram the exact same sequence over a hundred times. Move it out of the timB loop, and drop the `test_timB` function. Tested on Asus P8H61-M PRO, still boots. Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Make helper for write leveling sequenceAngel Pons
Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Run `read_mpr_training` before write trainingAngel Pons
Reference code does this, so follow suit. Tested on Asus P8H61-M PRO, still boots. Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename `read_training` functionAngel Pons
Given that it sets the receive enable mode bit in the GDCRTRAININGMOD register, it's clear that this is about receive enable calibration. Remove a potentially-outdated comment. Proper documentation will be written once code refactoring and various improvements are complete. Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD registerAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRCMDPICODINGAngel Pons
This register's layout makes no sense, so use bitfields for clarity. Tested on Asus P8H61-M PRO, still boots. Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Move constants out of for-loopAngel Pons
Most per-channel registers are programmed with the same values. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Use bitfields to program MCMAIN timingsAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clean up TC_OTHP writesAngel Pons
ODT stretch is configured for both slots in `dram_odt_stretch`. Also drop an unjustified OR, which is setting ODT stretch for one slot. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use one sequence for write levelingAngel Pons
In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Since `write_mrreg` is no longer used, it is necessary to handle address mirroring explicitly. This can be accomplished with the recently-added `ddr3_mirror_mrreg` function, which is also used in `write_mrreg`. Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22mb/google/zork: update berknip CHTC thermal settingKevin Chiu
Update APU CHTC thermal temperature protection point: Temperature limit(C'): 90 Update system config=2 to meet TDP 15W design. BUG=b:162377903 BRANCH=zork TEST=1. emerge-zork coreboot 2. check CHTC temperature by AMD utility Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-22soc/amd: move non-CAR linker scripts to common directoryFelix Held
AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-22sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDsAngel Pons
These two IDs are for Cougar Point and Panther Point, the previous generation of Platform Controller Hubs. So, drop their device IDs. Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-21util/amdfwtool: add missing zero-initialization for local variableFelix Held
Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21soc/amd: factor out vbnv_cmos_failed() into soc/amd/common/vbootFelix Held
Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11Subrata Banik
List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21mb/google/asurada: Get RAM code from ADC 3Yidi Lin
On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Asurada the RAM code can be read from ADC channel 3. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21cbfs: Add metadata cacheJulius Werner
This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-21nb/intel/sandybridge: Introduce `disable_refresh_machine` functionAngel Pons
The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop. Tested on Asus P8H61-M PRO, still boots. Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21intel/socket_441: Increase bootblock sizeJulius Werner
One mainboard using this socket has less than 20 bytes of space left in its bootblock, hindering development. Double the bootblock size to solve the problem. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I620c13eab53c3326a4f4660b63ed1dd0fc81f563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47585 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21Update vboot submodule to upstream masterJulius Werner
Updating from commit id 4c523ed1: vboot2: Add support for modexp acceleration to commit id 9d4053df: Revert "Reland: Clean up implicit fall through." This brings in 32 new commmits. Among the changes are restored support for older GCC/clang versions that do not support __attribute__((fallthrough)). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-21zork: Create gumboz variantKevin Chiu
Create the gumboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:173536689 BRANCH=zork TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_GUMBOZ Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21mb/google/zork: update DRAM table for dirinbozKevin Chiu
Add Hynix DDR4 DRAM, index was generated by gen_part_id H5ANAG6NCJR-XNC BUG=b:173480390 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21util: Add new DDR4 H5ANAG6NCJR-XNC for zork boardsKevin Chiu
Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=None TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-21mb/google/zork: update telemetry settings for WoomaxKane Chen
Update Woomax to improve the performance. BUG=b:168073070 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-21include/device/pci_ids: add PCI IDs for new AMD SoCsFelix Held
Change-Id: I0caea5627045b7855e2c5f3cb01d4fa21332788b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10John Su
Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC) activation. BUG=b:171531244 TEST=build and verify by thermal team Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20nb/intel/sandybridge: Rename loop variableAngel Pons
The `discover_edges_real` function actually tests a range of values for DQS PI and evaluates how the system responds. Rename the loop variable. Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/zork: Remove 50ms WIFI delayMartin Roth
As a part of trying to get our boot time as low as possible, any delays in the code should try to be refactored out. This removes the 50ms delay in the WIFI sequence by enabling power and putting the wifi module into reset in bootblock, then bringing it out of reset in ramstage. This is significantly longer than the 50ms requirement. The reset GPIO was already being set high in ramstage, so that code didn't need to be added. BUG=b:171513520 TEST=Boot on boards with different module types, WIFI works on both. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-20intel/fsp2_0: Add soc_validate_fsp_version for FSP version checkJohnny Lin
Only need to check this once so check it at romstage where the console is usually ready. Also define union fsp_revision to avoid code duplication. Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-11-20mb/google/volteer/var/elemi: Update gpioWisley Chen
1. Config EN_PP3300_SSD (GPP_B2) to gpo 2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11 3. WLAN_PERST_L (GPP_H10) change to GPP_H10 BUG=b:172630765, b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer/var/elemi: enable Genesys Logic GL9763EWisley Chen
Enable Genesys GL9763E as PCI-to-eMMC bridge. BUG=b:171467336 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I858c12151df5b6fc19132869317edfa1b090335d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-20mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESAPaul Menzel
Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing the connected network device also to be missing. This is caused by not configuring the third of the four PCIe General Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be exposed as one to four PCIe devices. So, enable it in AGESA but disable enumeration in coreboot. Otherwise, the serial console stops working in romstage after […] PCI: 00:15.1 bridge ctrl <- 0013 PCI: 00:15.1 cmd <- 06 PCI: 00:15.2 bridge ctrl <- 0013 PCI: 00:15.2 cmd <- 07 and the system hangs in the payload (SeaBIOS banner is shown on VGA attached monitor). TEST=Serial console and payload works, and Linux 5.10-rc2 configures PCIe bridge. Output of `lspci -t`: -[0000:00]-+-00.0 +-00.2 +-01.0 +-01.1 +-10.0 +-10.1 +-11.0 +-12.0 +-12.2 +-13.0 +-13.2 +-14.0 +-14.2 +-14.3 +-14.4-[01]-- +-14.5 +-15.0-[02]-- +-15.1-[03]----00.0 +-15.2-[04]----00.0 +-18.0 +-18.1 +-18.2 +-18.3 +-18.4 \-18.5 Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46527 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-24 15:27:27 +0000