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2020-07-09arch/arm/include/smp/spinlock.h: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I23f9aa969febe58dd3842e6a7cc75a6777b90b17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43255 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/samsung/exynos5420: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4f06e5e8a0d25308ba56d09a3d8b71f04dbd27b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-09soc/intel/broadwell/pcie.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ia314148abc900685d85aede3add480614fa8e99c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner
2020-07-09security/vboot/secdata_tpm.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ie01d65f80caf32a8318d5109ad48321661c5a87b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43213 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09security/tpm/tss/tcg-1.2/tss.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ifda2bbd87cd8ef5ec8e449d2c4d303be37b4d7c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43212 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/samsung/exynos5250: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4772680875b20308e57da073bbcdc4597aeed893 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09sb/intel/bd82x6x/pcie.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43216 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09sb/intel/i82801gx/pcie.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I0296cb4265c5b68ee9e11b140763b7d50d1da7ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43218 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09sb/intel/lynxpoint/pcie.c: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/amd/picasso: Always load and run display opromRob Barnes
The kernel requires the display oprom is loaded and ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:160560510 TEST=Boot Trembyle in developer mode and normal mode Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-09mb/asrock/b85m_pro4: Add Super I/O GPIO tableAngel Pons
Information taken from the boardviews. We are not configuring any GPIO in bootblock, but we may want to do so in the future. Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42404 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09mb/asrock/b85m_pro4: Properly select muxed functionsAngel Pons
The old values were completely out of whack. Use the same settings as vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites configured settings, so drop it from Kconfig to prevent conflicts. Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-09haswell: Drop GPIO indirection layersAngel Pons
This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09mb/google/slippy: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: Iec6dac1a271b22d6c09b4064a9e8a310e57026a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09mb/google/beltino: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: I536225351a0353298381c16cff25f39098c19bba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09sb/intel/lynxpoint: Drop RCBA reg script mechanismAngel Pons
It is no longer used anywhere. Drop it before it rots. Change-Id: I4bc3d5bd898058e575144a3c6c3fccb78dcff2e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09haswell: Turn RCBA configuration into a functionAngel Pons
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins. Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-09mb/siemens/mc_apl1: Use OPCODE menu set up of fast SPI driverWerner Zeh
The common fast SPI driver has a function to set up the SPI OPCODE menu. Use this function here instead of coding it again as it results in the very same register values being written. TEST=Compare register values in both cases and make sure they match. Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43166 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09mb/lenovo/t440p/romstage.c: Drop empty functionAngel Pons
There's a weak definition in chipset code that does nothing as well. Change-Id: I2531e8b9d48eb4a1a667f22a81bb082ec98c1199 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09soc/intel/baytrail/pmutil.c: Constify string arraysAngel Pons
This reduces the differences between Bay Trail and Braswell. The resulting binary changes, but it shouldn't matter. Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-09soc/intel/baytrail/pmutil.c: Do not hardcode num_bitsAngel Pons
This can result in accesses outside array bounds. Copy what Braswell does, which is slightly safer. Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-09soc/intel/baytrail: Align whitespace and commentsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-09soc/intel/baytrail: Rename "pmc.h" to "pm.h"Angel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-09mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik
Refer to commit 7736bfc TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/intel/braswell: Drop some BIOS_SPEW printk'sAngel Pons
This reduces the differences between Bay Trail and Braswell. Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-09soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMANDAngel Pons
The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops. Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-09libpayload: cbgfx: Replace bilinear resampling with LanczosJulius Werner
This patch improves the image resampling (scaling) code in CBGFX to use the Lanczos algorithm that is widely considered the "best" resampling algorithm (e.g. also the first choice in Python's PIL library). It is of course much more elaborate and therefore slower than bilinear resampling, but a lot of the difference can be made up with optimizations, and the resulting code was found to still produce acceptable speeds for existing Chrome OS UI use cases (on an Arm Cortex-A55 device, time to scale an image to 1101x593 went from ~88ms to ~275ms, a little over 3x slowdown). Nevertheless, if this should be too slow for anyone there's also an option to tune it down a little, but still much better than bilinear (same operation was ~170ms with this). Example images (scaled up by a factor of 7): Old (bilinear): https://i.imgur.com/ytr2n4Z.png New (Lanczos a=3): https://i.imgur.com/f0vKluM.png Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-09libpayload: Add simple 32.32 fixed-point math APIJulius Werner
struct fraction is slooooooooooow. This patch adds a simple 64-bit (32-bits integral, 32-bits fractional) fixed-point math API that is *much* faster (observed roughly 5x speed-up) when doing intensive graphics operations. It is optimized for speed over accuracy so some operations may lose a bit more precision than expected, but overall it's still plenty of bits for most use cases. Also includes support for basic trigonometric functions with a small lookup table. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Id0f9c23980e36ce0ac0b7c5cd0bc66153bca1fd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-09soc/amd/picasso: Remove I2C4Edward Hill
Remove I2C4 since it is a slave device used for USB-C mux control and should not be included with the other master devices. BUG=b:160624619 b:160292546 TEST=EC can communicate with AP mux I2C4 slave Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/amd/picasso: Add dummy spinlock for psp_verstageMartin Roth
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the spinlock code is missing. Add dummy spinlock code as the spinlocks aren't needed in the PSP. TEST=Build with CONFIG_CMOS_POST enabled. BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Do not select VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for VilbozFurquan Shaikh
This change drops the selection of VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for Vilboz since it did not have any build with pre-v3 schematics. Change-Id: I3919ad43e1dae95a4fa71073e83865e92f30dfec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Add helpers for v3 schematics and wifi power enableFurquan Shaikh
This change adds following two helper functions: 1. variant_uses_v3_schematics() - Check whether the variant is using v3 version of schematics. 2. variant_has_active_low_wifi_power() - Check whether the variant is using active low power enable for WiFi. In addition to this, Kconfig options are reorganized to add two new configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper functions to return `true` early without checking for board version. Eventually, when a variant decides to drop support for pre-v3 schematics, it can be dropped from selecting VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant decides to drop support for active high power enable for WiFi, it can be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Move GPIO_137 configuration to ramstageFurquan Shaikh
This change moves the configuration of GPIO_137 to happen in ramstage since there is nothing in coreboot that requires the state of write protect GPIO for zork. Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Do not share "write protect" information with depthchargeFurquan Shaikh
This change removes "write protect" entry from the list of GPIOs shared with depthcharge as done for other Chrome OS boards in CB:39318. Change-Id: Ibd39e8d6835e465b2ab5eebcc245e45db5d84deb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43222 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Disable PS/2 keyboard wakeupAngel Pons
This results in a wake from S5 as well. Since the PS/2 keyboard now works, this behavior is annoying and, therefore, undesired. Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42431 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Correct GP01 output levelAngel Pons
This allows the CPU fan tach signal to reach the Super I/O. Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42402 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetreeAngel Pons
Otherwise, there are complaints about it from the allocator. Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42401 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Correct Super I/O GPIOsAngel Pons
GPIO2 is not used as such, GPIO7 is though. Also relocate GPIO1 settings under the correct PnP device. Confirmed findings against boardviews. Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Expand Super I/O commentsAngel Pons
Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42399 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQAngel Pons
No wonder why the PS/2 keyboard was being detected as a mouse! Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42398 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Drop spurious LPC decode rangesAngel Pons
Only one generic decode range is needed for the HWM. Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42131 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asus/p8z77-v_lx2: Correct Super I/O GPIO settingsAngel Pons
Compared against superiotool dumps with vendor firmware. Still boots. Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42482 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/intel/baskingridge: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08sb/intel/lynxpoint: Program PM registers directlyAngel Pons
Perform the same operations as the RCBA reg script did, but directly writing the corresponding registers. Some of these operations could be simplified, but it is not done on this commit to ease verification. Change-Id: I4c3177ab14ca9bfa2e8d11c27fb249850183eee5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08sb/intel/lynxpoint: Factor out RCBA Function DisableAngel Pons
Comments stating that this was mainboard-specific were very wrong. Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08sb/intel/lynxpoint: Replace reg script with proper codeAngel Pons
Why use a Rube Goldberg machine to write and then read one register? Change-Id: I282c12f162b5ae69c40729903c09ae81a14c9761 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08haswell: relocate `romstage_common` to northbridgeAngel Pons
Other platforms do this as well. It will ease refactoring on follow-ups. Change-Id: I643982a58c6f5370c78acef93740f27df001a06d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08nb/intel/haswell: Drop unnecessary variableAngel Pons
The "normalized" boot mode is only used in a single place, so there's no need to use a variable. Also, reword the associated comment, which seems to be unnecessarily vague: the hardcoded assumptions are inside the MRC. Change-Id: I260d10f231f5de765d2675416d7047717d391d8f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08haswell: drop unused function parameterAngel Pons
The `chipset_type` parameter is ignored. Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08mb/google/slippy: Factor out common romstage settingsAngel Pons
There's no need to repeat the same values over four variants. Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 00:35:52 +0000