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2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-13crossgcc: Update make to latest version: 4.2.1Martin Roth
Change-Id: I4af90fd2fcfb2a823f9e6b1e975c71581f0b55e9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16164 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-13crossgcc: Add gnumake target so that make can be built directlyMartin Roth
Previously, make could be built as one of the crosgcc* targets, but there was no way to just rebuild make, as there is for IASL. - Add an independent target - gnumake. - Add gnumake to the help text. - Add gnumake to the list of NOCOMPILE targets (Not compiling coreboot) Change-Id: I4df25f2e209ca14944d491dbfb8e9b085ff7aca3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16163 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-13util/gitconfig: add cborg2cros.py scriptMartin Roth
This is a python script that does basically the same thing as the rebase.sh script, but in the other direction. rebase.sh takes files from the chromium tree (cros) and pulls them to the coreboot.org tree. cborg2cros, as the name implies, updates patches to go into the cros tree from coreboot. It adds the 'UPSTREAM: ' identifier to the start of the commit message, and uses the text '(cherry-picked from commit #####)' instead of 'Original-Commit-Id: #####' It also adds the 'TEST=', 'BRANCH=', and 'BUG=' lines if they aren't there. Change-Id: Ibad9a5f0d0d2c713cf08e103c463e2e82768c436 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15323 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-13chromeos: Make CHROMEOS_RAMOOPS_NON_ACPI a default for non-ACPI boardsJulius Werner
This patch enables the CHROMEOS_RAMOOPS_NON_APCI Kconfig option as a default across all non-x86 Chrome OS boards. CQ-DEPEND=CL:367905 BRANCH=None BUG=None TEST=See depthcharge CL. Change-Id: If14ef4f9b1bd480f2d52df3892c73059bb9b07d5 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8c3b74fb21aadd6de7af62f32fa98fc211d75085 Original-Change-Id: I16ff7f68762a995cd38e5fddaf6971d4b9f07e21 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/368010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16154 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-13Revert "gru: Show the current time on start-up"Julius Werner
This reverts commit 850e45f19f498eedd80da4a97a5ce641e2cec6d5. google_chromeec_init() is a weird function that can lead to confusing behavior. I'm not sure how it's meant to work on the boards that use it, but it causes problems on Kevin and other non-x86 boards have never used it either. It doesn't really do anything anyway (the EC works fine without an initial HELLO), so at best it's just a waste of time... let's take it back out. There's also no need to display the current time on every boot... other boards don't do that and the eventlog already fills the same purpose. Cut it out to avoid one extra host command overhead. BRANCH=None BUG=chrome-os-partner:55995 TEST=Recovery reasons now get correctly propagated across the EC reboot. Change-Id: Ic3b772780d4d05e362c269969e6e4e7069482bb6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 103d86e68cd164bea39aa1edc8668d80358edbde Original-Change-Id: I58fd5e6094e1c8cb6368e7a4569ab9231375fbc9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/367351 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/16153 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-13libpayload: head.S: Avoid clearing BSS (and heap) againJulius Werner
3 out of 4 architectures currently zero out the payload BSS in early assembly code, which is pointless since the code loading the payload has already done that (with a more efficient memset). ARM64 has never had any code like this and can run just fine without it. This also defeats the new optimization of moving the heap out of the BSS, since all three implementations assume that everything between _edata and _end is BSS. We should just take this out. Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16091 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-12libpayload: cbfs: Fix minor memory leak in some edge casesJulius Werner
cbfs_get_handle() allocates memory for a handle and doesn't free it if it errors out later, leaving the memory permanently leaked. Fix. Change-Id: Ide198105ce3ad6237672ff152b4490c768909564 Reported-by: Coverity Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16207 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-12Documentation: add start of documentation of the build systemPatrick Georgi
Change-Id: Ic4a4b4d71852bfe0b1fc52373e88d0a53b145844 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16150 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-12chromeec/acpi: add Tablet event and EC ACPI MEMjiazi Yang
Switch DPTF table when TABLET/NOTEBOOK mode changes 1. EC send EC_HOST_EVENT_MODE_CHANGE(29/0x1D) when mode changes 2. Host read current "physical mode" from EC ERAM BUG=chrome-os-partner:53526 BRANCH=master TEST=build glados Change-Id: I836d2b9d1a24c455c4b8d4b85f7edc19259d2f71 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9506c4c07e0f713c9a22a0231bc4255f6876783f Original-Change-Id: I5a3363ff9c958decb5aed1c85fc2a1ef6670931d Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/365991 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-12drivers/intel/fsp2_0: Fix FSP reset pathLee Leahy
Don't verify HOB list pointer or HOBs when FSP returns a reset request. BRANCH=none BUG=chrome-os-partner:56159 TEST=Build and run on Galileo Gen2. Change-Id: I6382f5ff92092623955806ebff340608c4ee156a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11soc/apollolake: enable access to RTC NVRAMRavi Sarawadi
FSP unconditionally locks parts of the NVRAM in the RTC. This change will enable coreboot to update the locking policy and be able to unlock the region BUG=chrome-os-partner:55944 TEST=Check 'crossystem dev_boot_usb=1' Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16144 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-11reef: Update chromeos.fmdFurquan Shaikh
1. Get rid of LBP2 partition 2. Shrink RO size 3. Increase RW-A and RW-B sizes 4. Increase RW_MRC_CACHE size CQ-DEPEND=CL:366793 BUG=chrome-os-partner:52127, chrome-os-partner:55699, chrome-os-partner:55778 BRANCH=None TEST=Compiles successfully. Boots to OS. Change-Id: Iad41d8cc7697e6d73f1aa2c699b0e8559349b77e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11soc/qualcomm/ipq40xx: Reduce the delay in I2C.Kan Yan
3ms delay was found in testing to be sufficient for qup_i2c_write_fifo_flush(), but 1 additional ms was added to give additional headroom. Change the Delay from 10ms to 4ms. BUG=b:28942403 TEST=Boot up Gale board and the TPM functions normally. BRANCH=None Change-Id: I6821e2a101cc44e11d74eb6a6215aa9b848ae8c6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d93520fab15c5695ea18db21d0f3b24a108f204d Original-Change-Id: I202f5b8a1ef62bb039c56ba5a25b48b205cf4a67 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/357961 Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Original-Reviewed-by: SARAVANAKUMAR SUDALAI <ssudalai@qti.qualcomm.com> Reviewed-on: https://review.coreboot.org/16126 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-11rockchip/rk3399: Add code to neuter Type-C PHY for firmware USBJulius Werner
The Rockchip RK3399 integrates a USB Type-C PHY in charge of things like SuperSpeed line muxing for rotated cable orientations in the SoC. While fancy, this is very complicated and we don't want to implement support for the whole thing in firmware. The USB Type-C standard has intentionally been designed in a way that the USB 2.0 (HighSpeed) lines always "just work" in any orientation (by just shorting different pins in the connector together) so that simple use cases like ours can get basic USB functionality without much hassle. However, a semi-configured Type-C PHY can confuse USB 3.0 capable devices into thinking we're actually supporting SuperSpeed, and fail at that rather than establishing a reliable HighSpeed connection. This patch sets enough bits in the Type-C PHY to electrically isolate the SuperSpeed lines from the connector so that the connected device isn't going to get any fancy ideas and reliably falls back to USB 2.0. Also clean up the rest of the USB code while we're at it: avoid writing a few bits that are already in the right state from their reset values anyway, or reading values whose content we already know for this SoC. Rename the USB controllers to the name actually used in the Rockchip documentation (USB OTGx) rather than the name blindly copied from Exynos code (USB DRDx). BRANCH=None BUG=chrome-os-partner:54621 TEST=Plug a USB 3.0 Patriot Memory stick into both ports in all orientations, observe how it gets reliably detected now (safe for some known hardware issues on my board). Change-Id: Ifce6bcddd69f2e8f2e2a2f48faf65551e084da1e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c526906f998bf66067d3addb8b3d3a126c188b1e Original-Change-Id: Ie80a201a58764c4d851fe4a5098a5acfc4bcebdf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366160 Original-Reviewed-by: liangfeng wu <wulf@rock-chips.com> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: <515506667@qq.com> Reviewed-on: https://review.coreboot.org/16125 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-11arch/riscv: Fix the page table setup codeJonathan Neuschäfer
In particular: - Fix the condition of the loop that fills the mid-level page table - Adhere to the format of sptbr Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16120 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-11arch/riscv: Update encoding.h and dependent filesJonathan Neuschäfer
I copied it from commit e10d2def7d of spike and made sure the copyright header is still there. Change-Id: Ie8b56cd2f4855b97d36a112a195866f4ff0feec5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-11lenovo/x60: add info message if dock is presentAlexander Couzens
Change-Id: I5a6d41f815f65719780499fa18c131311a9dc8f7 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16136 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-11lenovo/x60: add GPIOs initialisation before dock checkAntonello Dettori
Add GPIOs initialisation before dock check. Needed in order to properly detect the presence or absence of the lenovo dock. Previously the check always reported the dock as connected and currently it always reports it as disconnected since the GPIOs are not properly initialised during the check. Tested and confirmed working. Change-Id: I7fbf8c2262a1eb5dee9cbe5e23bf44f7f8181009 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16139 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-11vendorcode/intel/fsp: Add fsp 2.0 header files for skylake and kabylakeRizwan Qureshi
Add FSP 2.0 header files, these files are common for Skylake and Kabylake, name the folder as skykabylake to signify the same. Change-Id: I71b43a59c9a9b0adf1ee48285e4a72e24a13df2d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-11build system: Print the content of all regions we add files toPatrick Georgi
That's more useful than just COREBOOT for more complex scenarios Change-Id: I93cd686d698799a3331ca2ea487cd6efb304caa0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16143 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11build system: drop -cbfstool-opts variable supportPatrick Georgi
It was a band-aid that isn't required any more. Change-Id: Ib1793ae8fe25eecf9bd5ab8e5feef0d9380b43c2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16142 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11intel/fsp1_1: Use new per-region position overridePatrick Georgi
It cooperates better with the file sorting heuristic. Change-Id: I1c071243720352970dd2c4c2afed12451f91dcaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16141 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11build system: allow overriding file position and alignment per regionPatrick Georgi
To override fallback/foo's position or alignment in region BAR, use fallback/foo-BAR-{position,align} = 0x1234 Like for the global settings, specifying both isn't allowed because that's rather pointless. Change-Id: I94f41ebc9f35108267265df4164f23b70e3d0bf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11build system: remove early stage cbfs-file sortingPatrick Georgi
They're now sorted later in the process after the per-region file lists are determined. Change-Id: I0bba381d09dc4b99e2fe5cae16ff7ffcb5b3aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16138 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11build system: order per-region files to optimize placement successPatrick Georgi
Make sure that files with a fixed position are placed first (whose order doesn't matter: either they collide or they don't), then all aligned files (where we just hope that the right thing happens) and finally the files with no further requirements (again, hope). It's still a pretty good heuristic given a typical coreboot image. The global sorting that happens earlier in the build flow will be removed in the future to make room for per-region requirements. Change-Id: I269c00b2ece262c95d310b76a6651c9574badb58 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16137 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11intel/amenia: Add MAINBOARD_FAMILY for ameniaBora Guvendik
BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I66178cc75872f14941434081d9650a569a084d04 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16135 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11intel/amenia: set default value for BOOT_MEDIA_SPI_BUSBora Guvendik
BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I60d411482812d98cb8dd11d66b0fc96ea9bae895 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16134 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11intel/amenia: Select UART_FOR_CONSOLE for ameniaBora Guvendik
Set default value for UART port BUG=chrome-os-partner:51844 TEST=Boot to chrome and check console Change-Id: I5e76066e0ff531303595dcd5a99f2f8db379e89b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16133 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11intel/amenia: Update flash size to 16MBBora Guvendik
Update flash image size to 16MB and update image layout in flashmap descriptor file. BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: Ibdfb2949d06aedc38ddcef1078c2d14abcfa2dac Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16083 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11soc/intel/common: Add support for serial console based ACPI debugSubrata Banik
This patch enables serial debug functionality for ASL code based on UART type(legacy/LPSS). From Skylake onwards all Intel platform uses LPSS based UART for serial console hence provide option to redirect ASL log over LPSS UART. Example: Name (OBJ, 0x12) APRT (OBJ) APRT ("CORE BOOT") Output: 0x12 CORE BOOT BUG=none BRANCH=none TEST=Built and boot kunimitsu to ensure to be able to get ASL console log. Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/16070 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11fsp_Broadwell_DE: Do not set IRQ3 and IRQ4 to levelKevin Paul Herbert
When booting Linux as a coreboot payload, serial access does not work properly. This is because the setup code erroneously sets IRQ3 and IRQ4 to level. The UART on Broadwell is 8250/16550 compatible, thus ISA and edge-triggered. This change is not necessary on the non-FSP version of Broadwell support. The non-FSP version does not set these IRQ overrides. Fix verified booting Linux 4.6.0-rc2 on Intel Camelback Mountain CRB, using Intel FSP 1.0. Change-Id: I17b466676e7f4891c3e75ce6208e1580c9eaf742 Signed-off-by: Kevin Paul Herbert <kevin@trippers.org> Reviewed-on: https://review.coreboot.org/16065 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-11buildgcc: printf no-color before quitingZheng Bao
On some kind of terms (shell in emacs), the color-ctrl letters don't work. The backspaces can not delete correct number of letters. So we don't print color-ctrl letters in loop. Change-Id: I1f1729095e8968a9344ed9f1f278f7c78f7110e9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/16066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10rockchip/common: Set weekday to unknown in rtc_get()Martin Roth
Prior to this patch, time->wday was not being initialized in rtc_get(), but was still being used by rtc_display() to print a day. Set to -1 which gets printed as "unknown ". Fixes coverity issue 1357459 - Uninitialized scalar variable Change-Id: Idecb7968f854df997b58a342e1a06a879f299394 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15899 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-08-10soc/intel/quark: Switch to using serial routines for FSPLee Leahy
Switch from passing FSP the serial port address to passing FSP the serial port output routine. This enables coreboot to use any UART in the system and also log the FSP output. TEST=Build and run on Galileo Gen2 Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10drivers/intel/fsp2_0: Add fsp_write_line functionLee Leahy
Add fsp_write_line function which may be called by FSP to output debug serial data to the console. TEST=Build and run on Galileo Gen2 Change-Id: If7bfcea1af82209dcdc5a9f9f2d9334842c1595e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10drivers/intel/fsp1_1: Add fsp_write_line functionLee Leahy
Add fsp_write_line function which may be called by FSP to output debug serial data to the console. TEST=Build and run on Galileo Gen2 Change-Id: Ib01aef448798e47ac613b38eb20bf25537b9221f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10console: Add write line routineLee Leahy
Add write line routine which is called indirectly by FSP. TEST=Build and run on Galileo Gen2. Change-Id: Idefb6e9ebe5a2b614055dabddc1882bfa3bba673 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16127 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10build system: change addition order of files to go by regionPatrick Georgi
Instead of adding each file in all requested regions, sort by region, then by file. This is in preparation of per-region file options (eg. position, alignment) Change-Id: Ide09a1c8840279380294a059bbd5d2f9f0cba780 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16130 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10util/cbfstool: Initialize elf_writer pointer to avoid crashJonathan Neuschäfer
If some error happens in cbfs_payload_make_elf, the code jumps to "out", and elf_writer_destroy(ew) is called. This may happen before an elf writer is allocated. To avoid accessing an uninitialized pointer, initialize ew to NULL; elf_writer_destroy will perform no action in this case. Change-Id: I5f1f9c4d37f2bdeaaeeca7a15720c7b4c963d953 Reported-By: Coverity Scan (1361475) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16124 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10Makefiles: Use $(MAINBOARD_DIR) instead of $(CONFIG_MAINBOARD_DIR)Martin Roth
The variable MAINBOARD_DIR already has the quotes stripped off. Change-Id: Ib434ce92bdbc49180fb3f713b26d65ba4cf8c441 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/16117 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-10Makefile.inc: Strip CONFIG_DEVICETREE quotes at top of makefileMartin Roth
Minor change - Instead of stripping the quotes from CONFIG_DEVICETREE inline, add it to the location where we normalize all the other Kconfig variables. Change-Id: Idbc58179c7b45160afef7d7e44f9b3b334f8c4a7 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/16116 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-10google/reef: Add mainboard handler function for gpio SMIShaunak Saha
This patch adds mainboard_smi_gpi_handler which handles the SMI event. This can happen in situations like lidclose and system goes to shutdown. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10soc/apollolake: add GPIO SMI supportShaunak Saha
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS register. This patch also sets the SMI_EN bit in enable register for each community based on GPIOROUTSMI bit in gpio pad. When SMI on a gpio happens status needs to be gathered on gpio number which is done by reading the GPI_SMI_STS and GPI_SMI_EN registers. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-10elog: Ensure eventlog will always get initialized when configured inJulius Werner
Commit 0d9cd92e (chromeos: Clean up elog handling) removed the individual elog_init() calls from mainboards that did them and automated adding certain events through the boot state machine. Unfortunately, the new code would sometimes not log any specific event at all, and thereby also never call elog_init() (through elog_add_event()) which adds the "System boot" event. We can assume that any board that configures the eventlog at all actually wants to use it, so let's just add another call to elog_init() to the boot state machine so we can ensure it gets called at least once. BRANCH=None BUG=chrome-os-partner:56001 TEST=Booted Kevin, confirmed that eventlog code runs again. Change-Id: Ibe7bfc94b3e3d11ba881399a39f9915991c89d8c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16118 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-09drivers/elog: provide return status for all operationsAaron Durbin
Instead of relying on global state to determine if an error occurred provide the ability to know if an add or shrink operation is successful. Now the call chains report the error back up the stack and out to the callers. BUG=chrome-os-partner:55932 Change-Id: Id4ed4d93e331f1bf16e038df69ef067446d00102 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16104 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09drivers/elog: clean up SMBIOS related codeAaron Durbin
Don't conditionally compile parts of the code. The unused pieces get culled by the linker, and the #if's just clutter things up. BUG=chrome-os-partner:55932 Change-Id: Ic18b2deb0cfef7167c05f0a641eae2f4cdc848ee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09drivers/elog: consolidate checks in elog_find_flash()Aaron Durbin
There were checks against global variables trying to determine failing cases of elog_find_flash(). Instead move the checks into elog_find_flash() and return value indicating failure. A minimum 4KiB check was added to ensure the eventlog is at least that size which makes the heuristic checks cleaner. BUG=chrome-os-partner:55932 Change-Id: I4d9d13148555e05d4f217a10f995831a0e437fc3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16101 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-09google/gru: Fix rk3399-gru write protectDouglas Anderson
The write protect GPIO is active high, not active low. After fixing I can see this after removing the write-protect screw: $ crossystem | grep wpsw_boot wpsw_boot = 0 Putting the screw in shows: $ crossystem | grep wpsw_boot wpsw_boot = 1 Caution: this CL contains explicit material. It explicitly sets the pullup on the WP GPIO even though that's the boot default. BRANCH=None BUG=chrome-os-partner:55933 TEST=See desc. Change-Id: I23e17e3bbbe7dcd83e81814de46117491e61baaa Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e6969f4be42c00c6e88bbb14929cf0454462ad21 Original-Change-Id: Ie65db9cf182b0a0a05ae412f86904df6b239e0f4 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366131 Original-Tested-by: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09drivers/elog: remove unnecessary global stateAaron Durbin
There were 3 variables indicating the state of the event log region. However, there's no need to keep track of those individually. The only thing required is to know is if elog_scan_flash() failed. There's no other tracking required beyond that. BUG=chrome-os-partner:55932 Change-Id: I88ad32091d3c37966a2ac6272f8ad95bcc8c4270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16100 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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