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2020-10-09mrc_cache: Change mrc_cache_load_current to return size of entryShelley Chen
Modify mrc_cache_load current to return the size of the mrc_cache entry so that caller will know what the actual size of the data returned is. This is needed for ARM devices like trogdor, which need to know the size of the training data when populating the QcLib interface table. BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a Change-Id: Ia314717ad2a7d5232b37a19951c1aecd7f843c27 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-08mb/google/zork/berknip: Increase eMMC initial clock frequencyRob Barnes
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot Berknip w/ eMMC to OS. BRANCH=zork Change-Id: I5d55f55b8208b4dc3fbdc9d1ec6333f9e211e3fd Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45931 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08zork/var/ezkinil: Add micron-MT40A1G16KD-062E-E in SPD table for Ezkinil.Lucas Chen
Current Ram_Id: 0011 MT40A1G16KNR-075-E never be built before. Remove it and change use micron-MT40A1G16KD-062E-E for ram_id:0011. BRANCH=zork BUG=b:159316110 TEST=run gen_part_id then check the generated files. Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I28fc39f17e06ecd39f6567613e6ff5919becb2fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45810 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08mb/google/zork/ezkinil: Increase eMMC initial clock frequencyRaul E Rangel
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot Ezkinil w/ eMMC to OS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa Reviewed-on: https://review.coreboot.org/c/coreboot/+/45852 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08mb/google/zork/morphius: Increase eMMC initial clock frequencyRob Barnes
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot on morphius with and without patch, confirm ~7ms improvement BRANCH=zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I7f6efd3d5839f154f2487a07654be8e35634bbbc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45932 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08device: Clarify use of `config_of()`Nico Huber
We don't want unnecessary die() calls to spread throughout coreboot. Chances are high that we'd add a NON_FATAL_DIE Kconfig eventually. Change-Id: I01c7efdf23672bad3a195b7dc1565a3cc8a087bd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46046 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08mb/google/dedede/variants/drawcia: Update TSR1 passive trip temperatureSumeet R Pawnikar
Update TSR1 passive trip temperature BUG=b:169691800 BRANCH=None TEST=Built and tested on dedede system Change-Id: I172391daca981d5591fa9cc5eacad92521dd0dc5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-10-08mb/google/dedede: Configure VR in devicetreeMeera Ravindranath
BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I3ea32218040263f0abef9b9dd4c52efb16289fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45825 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel/jasperlake: Add VR Configuration settingsMeera Ravindranath
This CL fixes the CPU Throttling issue. BUG=b:167472333 TEST=Build and boot dedede and observe the slope and offset values getting updated in the fsp debug log Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-08Revert "soc/intel/jasperlake: Disable PAVP UPD"Nico Huber
This reverts commit 69589294c205b616e80cafbbfb0b33e105a75386. No reason was given why this should deviate from the other platforms and the author can't explain it. Change-Id: I2e8d6f9bd4ebba69b6f7cdd9a1c5d08aaf2e798f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMXChristian Walter
Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08security/intel/txt: Print chipset as hex valueChristian Walter
Print chipset as hex value in order to make it more readable. Change-Id: Ifafbe0a1161e9fe6e790692002375f45d813b723 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08mb/google/volteer: disable TBT if no USB4 hardware availableNick Vaccaro
Implement mainboard_silicon_init_params() to allow for disabling of TBT root ports if the device does not have usb4 hardware. Add code to mainboard_memory_init_params() to disable memory-related settings associated with TBT in cases where no usb4 is available. BUG=b:167983038 TEST=none Change-Id: Iab23c07e15f754ca807f128b9edad7fdc9a44b9d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-08lib/fw_config: change BOOT_STATE_INIT_ENTRY to be BS_DEV_INIT_CHIPSNick Vaccaro
Make boot state init run before the init_chips code. This allows for correcting tbt settings at a stage earlier than devicetree parsing. BUG=b:167983038 TEST=none Change-Id: I8364746ba311575e7de93fa25241ffef7faf35b4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45961 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17Johnny Lin
Override smbios_fill_dimm_locator for type 17 Locator and Bank Locator. Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS is always enabled and it makes the code cleaner. One sample type 17 table displayed as below: Handle 0x0010, DMI type 17, 40 bytes Memory Device ... Locator: DIMM F0 Bank Locator: _Node0_Channel5_Dimm0 Tested=On OCP Delta Lake, the Locator and Bank Locator strings are expected. Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17Johnny Lin
For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fieldsJohnny Lin
The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17. Tested=On OCP Delta Lake, verify the values are expected. Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel/xeon_sp/cpx: correct GSI bases for IO APICsJonathan Zhang
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct the coreboot assignment of GSIs for IO APICs. Without this patch, there are following target OS boot messages: [    1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [    1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119] After this patch, the boot messages are: [ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127 Also without this patch, there is boot stability issue. About one in 20 reboots, the target OS fails to boot with following failure: [ 4.325795] mce: [Hardware Error]: Machine check events logged [ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d The MCE error happens in bank 9. The Model specific error code shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something goes wrong when cache write back to mmio. It is a generic transaction type error in level 2. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 releaseJonathan Zhang
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs. Update FspmUpd.h and HOB header files. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/mediatek: Add function to raise the CPU frequency of MT8192Weiyi Lu
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq(). Implement mt_pll_raise_little_cpu_freq() in MT8192. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-08lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEWAngel Pons
There's no need to make so much noise when writing IOBP registers. Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-08sb/intel/lynxpoint/acpi/serialio.asl: Enable DMA channelsAngel Pons
Broadwell does this, so do it on Lynx Point too. Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-08util/intelp2m: Add output files to .gitignoreMaxim Polyakov
Change-Id: I50a783424b0d244eb824db9cd73738108f800003 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08mb/intel/adlrvp: Add initial ADL-P mainboard codeSubrata Banik
List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08mb/intel/{jslrvp,tglrvp}: Remove non-existent 'subdirs-y += ../common'Subrata Banik
TEST=Able to build TGLRVP and JSLRVP. Change-Id: Ie07df9f59015092a4c2a27b1451f0d556c70f0d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-08soc/intel: Make use of common gfx.aslSubrata Banik
Add gfx.asl file for all IA SOCs to allow for graphics-related ACPI devices and methods. TEST=Able to build and boot TGL platform Dump and disassemble DSDT, verify GFX0 device present as below Device (GFX0) { Name (_ADR, 0x00020000) // _ADR: Address } Change-Id: I5560e900a77872552df1064dc3b7a8148e35d682 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/common/block/acpi: Factor out common gfx.aslSubrata Banik
This patch moves gfx.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot CML platform. 1) Dump and disassemble DSDT, verify GFX0 device present inside common gfx.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ie34181a6783d348265cf4299dec5c41e7f4f736f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/amd/picasso: Remove xhci0_force_gen1 from soc configChris Wang
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead. The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1. Now variant can use the usb3_port_force_gen1 to customize which port it needs to limit. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-08mb/google/zork: Set USB3 port to force gen1 for morphius and ezkinilChris Wang
In morphius, the USB3 typeA port needs to set to gen1, and for ezkinil all the USB3 ports should force to gen1. So set the corresponding setting to usb3_port_force_gen1 to force USB3 to Gen1. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-08soc/amd/picasso: Add UPD for support force USB3 to Gen1 by portChris Wang
Add UPD usb3_port_force_gen1 for support USB3 port force to gen1. BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-10-08rules.h: change verstage name if it starts before bootblockKangheui Won
VBOOT_STARTS_VEFORE_BOOTBLOCK indicates that verstage starts before bootblock. However "cbmem -1" will first try to match "bootblock starting" to find out the beginning of console for current boot. Change ENV_STRING for verstage to "verstage-before-bootblock" in the case and add regex in cbmem utility to grab it. BUG=b:159220781 TEST=flash and boot, check `cbmem -1` BRANCH=zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ica38f6bfeb05605caadac208e790fd072b352732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-08soc/amd/picasso: Print values from PSP transfer bufferMartin Roth
The PSP will now pass us data on the PSP boot mode and the production silicon level. Print these values out to save in the log. These definitions are in a vendorcode include directory that was previously only included in verstage. Add the include directory to all stages. BUG=b:170237834 TEST=Build & Boot - See values printed. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com>
2020-10-08soc/amd/picasso: Refactor transfer buffer checkMartin Roth
The transfer buffer check had gotten large enough to deserve a function of its own, so break it out. BUG=None TEST=Build Branch=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/amd/picasso: Die if the workbuf is missing two boots in a rowMartin Roth
BUG=b:169199392 TEST=Corrupt vboot signature to force an error, see that the system halts instead of rebooting forever. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45964 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07trogdor: Remove Limits config entry.mkurumel
Change-Id: Id913fc4a89ad5eff6b3487354ff8be7661539fe5 Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-07sc7180: Remove LIMITS_CFG loading in romstage.mkurumel
LIMITS_CFG is not used/required by trogdor. Supporting this requires an FMAP partition as well as code, removing this support saves space and maintenance headaches. Change-Id: I9f57f5b520599ba6d708c91df9851e0e86b4b6c0 Signed-off-by: Manideep Kurumella <mkurumel@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45704 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07mb/google/zork: Add EC device wakeup for morphiusJosie Nordrum
Add support for trackpoint wakeup from S3 by adding device events to mainboard and defining for morphius. BUG=b:160345665 BRANCH=zork TEST=tested trackpoint wake from S3 on morphius DVT Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I982f0f4b60fbaeb389774531e1dee83da77cb8a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-07amd/picasso/psp_verstage: use cbmem consoleKangheui Won
psp_verstage uses separate printk implementation, which does not include code to add console output to cbmem. Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem. BUG=b:159220781 TEST=build BRANCH=zork Change-Id: I63ba5814903565c372dbeb50004565a371dad730 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46059 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07Update vboot submodule to upstream masterKangheui Won
Updating from commit id 4bb06cc1: COIL: Change denylist to blocklist to commit id 4c523ed1: vboot2: Add support for modexp acceleration This brings in 10 new commmits. Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-07amd/picasso/psp_verstage: Add modexp svc wrapperKangheui Won
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 BRANCH=zork TEST=build verstage for zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-07vc/amd/fsp: Update the svc call header for the Mod Exp SVCMartin Roth
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45942 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07drivers/intel/wifi: Drop call to pci_dev_initFurquan Shaikh
`pci_dev_init()` is used to load and run option ROM on VGA class devices (PCI_CLASS_DISPLAY_VGA). WiFi device is not a VGA class device and hence the call to `pci_dev_init()` is not required. This change drops the call to `pci_dev_init()` from `wifi_pci_dev_init()` in Intel WiFi driver. BUG=b:169802515 BRANCH=zork Change-Id: I6588ea0a5c848904088d05fd1cbdf677b2dc8ea9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-07drivers/wifi/generic: Use pci_dev_* operations for device opsFurquan Shaikh
WiFi devices supported by the generic WiFi driver are PCIe devices which need to be managed using the standard pci_dev_* operations to read, set and enable resources. This change updates the device_operations structure `wifi_generic_ops` to use the standard pci_dev_* operations for these devices. BUG=b:169802515 BRANCH=zork Change-Id: I8b306259e205ecb963c0563000bd96ec6b978b8b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-06templates: add an empty SPD to SPD_SOURCESPaul Fagerburg
Add an empty SPD in SPD_SOURCES when creating a new variant of hatch, volteer, waddledee, or waddledoo, so that coreboot can build successfully. For variants that use spd_tools, add an empty mem_parts_used.txt so that the developer can add the supported memory parts and regenerate the Makefile.inc with the correct SPD references. Add an empty SPD for LPDDR4x for waddledee and waddledoo to use. BUG=b:169422833 TEST=create a new variant of hatch, volteer, waddledee, and waddledoo. Observe that each one succeeds. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-06drivers/ipmi/ocp/ipmi_ocp.c: Clean up includesMarc Jones
Remove #include "chip.h", which is not needed and causes a build problem in a later change. Alphabetise the #includes. Add <types.h>. Change-Id: If19ccd144bd352a196adccd75f9f6f139eae4e4a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45968 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/skx: Move get_srat_memory_entries()Marc Jones
Prepare for common ACPI code. Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where the other srat ACPI functions are located. Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/cpx: Don't use SCI defineMarc Jones
Continue preparations for common ACPI code. Add code from skx and common/acpi to check the SCI register instead of using a define. Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/skx: Move soc specific ACPI functionsMarc Jones
Prepare for common ACPI code. Move skx soc ACPI functions to a separate file. Change-Id: I12526c17a0dcbc45494ae19c8abaf8bf9a1eab47 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/cpx: Move soc specific ACPI functionsMarc Jones
Prepare for common ACPI code. Move cpx soc ACPI functions to a separate file, soc_acpi.c Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/skx/: Reorder acpi.c functionsMarc Jones
Reorder the functions to make it easier to compare with soc/intel/common/block/acpi/acpi.c and cpx/acpi.c. Move the xeon_sp specific functions to the top. Change-Id: I7bc147781261c2fc39374f5bfe3ba79047b4993a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 13:43:23 +0000