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This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp
Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The CPU <--> CPU HT wiring on this board has only been validated
to 2.6GHz. While higher frequencies appear to function initially,
and in fact function when only one CPU package is installed, dual
CPU package systems will lock up after around 6 - 12 hours of uptime
due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks.
If applications are not being used that stress the coherent fabric,
then the uptime before hang may be much longer. Users attempting
to overclock the HT links are advised to "burn in test" the HT links
by running memtester locked to a node with no local memory installed.
Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12064
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12065
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
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The BKDG recommends the use of an antiphase window detection
algorithm to ensure that the DQS data eye is properly centered.
TEST: Booted both with DIMMs known to move the data eye into the
prior clock phase and DIMMs known to keep the data eye in the
current clock phase.
Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12059
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually
existed in the coreboot codebase. I didn't see anything that it might
have been a typo of.
Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12563
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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The odd rank of each DIMM could experience data corruption due to
incorrect DQS training. Fix the DQS training algorithm by executing
the relevant portions of the training algorithm on the odd ranks.
Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Also fix incorrect Trfc[0-3] value on Family 15h.
Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12565
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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That allows this special case to become a normal cbfs-files instance,
too.
Change-Id: I896ffebe4cec64c9c11605b4f09c7790e5419928
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12539
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I37b716acb305a79614cea184f57b8488111eab7a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use cbfs-files-y to deal with some of the manually added cbfs files,
providing more structure to that part of the build.
Change-Id: Iee1b8fec81dfa5e5f0e55637a62e5f69bd0257ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12538
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Idd05a552762be92d0d93b357b96442b25a614757
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12537
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add files with fixed positions, then files with alignment requirements
and finally those that can reside everywhere to prevent the most obvious
collisions.
This isn't perfect yet (the "aligned" group may need some additional
sorting), but should avoid the worst instances ("free floating" files
allocating space required by fixed location files, for example).
Change-Id: I871e1a92ad90e63fc4e299fe1b228b4b00a35930
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12536
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The silicon in control of CC6 appears to contain minor bugs
and / or deviations from the BKDG; through trial and error
it was found that these issues can be worked around by reserving
the entire possible CC6 save region, regardless of currently
installed node count.
Change-Id: If31140651f25f9c524a824b2da552ce3690eae18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The more generic 8250 driver can handle both port-mapped and memory-
mapped 8250-compatible UARTs, with different register sizes. Thus, a
separate driver for MMIO32 is not needed.
The generic 8250 driver was tested to work for both output and input,
on Apollolake SoC, which only presents an MMIO32 UART.
Change-Id: Idab766588ddd097649a37de92394b0078ecc660a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12524
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The missing brackets caused other registers, including the IO APIC
enable bit (EAN in OIC) to be overwritten. Bug introduced by
bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer)
Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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By adding the version number of tools, we can help people keep up to
date with their tool versions. This will be used now to determine
whether the IASL version being used is the version supported by
coreboot.
Change-Id: I24a68b01c819871f90403869570125e71b96bd70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Add an empty Operating Region for the empty _REG method
- Move Named objects out of _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
Fixes these items:
dsdt.aml 1449: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1458: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I801a84468097687c91d6ee3f44cec06243355fac
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Add specific build targets for IASL & CLANG and help for those targets
- Consolidate tool target .PHONY entries
Change-Id: If2960d75310495d9e486b3a08808463a2ff0c644
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12541
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change leading spaces to tabs.
Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12546
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
Fixes IASL Warning and remark:
dsdt.aml 1451: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1460: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I4aa59468a89c4013146ab34004476a0968c60707
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12521
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Mingw doesn't have that this function.
Change-Id: I640ea61ff24fba812e3f10771dd7e468dcfc63dd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/11724
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This makes the make process look like the one inside
of coreboot's build system.
Change-Id: I48be2df39cad47644e16ce583b27c33a1da81fc3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12509
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Fixes early fault problem on Fam0Fh introduced in
Change I8e01a4ab68b463efe02c27f589e0b4b719532eb5,
commit 991f18475c951dcd728eb8550b10dd62938b1770.
Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/12528
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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Change-Id: I1698c9b9b1840d254115821f3c0e76b7211e9056
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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PSP2 is for Combo BIOS, which is the idea that one image supports 2
kinds of APU.
The PSP2 feature is for the future, not for current products.
The newest document about PSP2 is not available. I made it from the
draft code I made when I was in AMD.
Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12527
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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If any path in a method returns a value, IASL expects that all paths
within that method will return a value.
Presumably, the ATPX would not need a return value if Arg0 is anything
other than 0, so just return a zero.
- Serialize ATPX method to make IASL happy. This means that it can
only be used by one thread at a time.
Fixes these issues:
dsdt.aml 2581: Method (ATPX, 2, NotSerialized) {
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 2581: Method (ATPX, 2, NotSerialized) {
Warning 3115 - ^ Not all control paths return a value (ATPX)
Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12518
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Touchpad and Touchscreen _CRS methods do not return an interrupt
value if the I2c busses that the devices are on are not in PCI mode.
Previously they didn't return any value if they weren't in PCI mode.
This patch has them return an empty resource template.
Fixes these warnings:
dsdt.aml 2813: Method (_CRS)
Warning 3115 - ^ Not all control paths return a value (_CRS)
dsdt.aml 2813: Method (_CRS)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _CRS)
dsdt.aml 2832: Method (_CRS)
Warning 3115 - ^ Not all control paths return a value (_CRS)
dsdt.aml 2832: Method (_CRS)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _CRS)
Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Affects these mainboards:
- lenovo/g505s
- google/parrot
- hp/pavilion_m6_1035dx
Fixes IASL notice for this specific instance:
dsdt.aml 1952: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
Change-Id: Id297cdea35d43f51887f798a9983629343c2313a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12513
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
Fixes IASL Warning:
dsdt.aml 1362: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Fixes IASL remark:
dsdt.aml 1353: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12515
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fixes these remarks:
Object is not referenced (Name is within method [_CRS])
The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method. Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.
Change-Id: I54ab3ad9ed148fdd24e8615d83bc8ae668d1dbff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Ignore output files for the new utilities amdfwtool and intelvbttool
- Ignore xml files for 'make what-jenkins-does'
- Ignore build files from libpayload's 'make install'
Change-Id: Ie4f1c9bf7dc597f7600c8bda0c6fad5f40acf7f8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Currently running 'make help' just gives help for the kconfig targets.
This adds help for common coreboot and toolchain targets. It stops
printing some of the less common kconfig targets, but still leaves
them in the makefile as documentation.
Change-Id: I2a00fcbc06f05dc4029a91f3dff830c19e4d1329
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12458
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If any path in a method returns a value, IASL expects that all paths
within that method will return a value.
Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.
Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 - ^ Not all control paths return a value (MHKP)
This was the only IASL warning in most lenovo mainboards.
Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The SIO device needs to provide an _ADR object with the IO
address as well as the address in the OperationRegion.
ACPI provides two different Resource Descriptor Macros to describe the
I/O areas required for a device. The FixedIO macro is only valid for
10-bit IO addresses. Use the IO macro instead.
Thank you to recent IASL that allows for addition in the ASL file. :)
Fixes these warnings:
dsdt.aml 2276: Device (SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 2390: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
dsdt.aml 2394: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
Lumpy now compiles its ASL tables with no warnings. Re-enable
Warnings as errors.
Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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FSP 1.0 has a fixed-size temporary cache size and address and the entire
cache is migrated in the FSP FspInitEntry() function.
Previous code expected the symbol _car_data_start to be the same as
CONFIG_DCACHE_RAM_BASE and _car_data_end to be the same as
_preram_cbmem_console.
FSP 1.0 is the only one that migrates _preram_cbmem_console.
Others leave that where it is and extract the early console data in
cbmemc_reinit(). Special handling is needed to handle that.
Commit dd6fa93d broke both assumptions and so broke the timestamp table
and console.
The fix is to use CONFIG_DCACHE_RAM_BASE when calculating the offset and
to use _preram_cbmem_console instead of _car_data_end for the console
check.
Change-Id: I6db109269b3537f7cb1300357c483ff2a745ffa7
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12511
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
dsdt.aml 1445: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1454: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If the timestamp table gets corrupted (separate issue), the
timestamp_sync_cache_to_cbmem() function may add a large number of bogus
timestamp entries.
This causes a flood of "ERROR: Timestamp table full". With logs going
to a serial console, this renders the system essentially unbootable.
There really isn't a need to log that more than once, so log it when the
last slot in the timestamp table is filled.
Change-Id: I05d131183afceca31f4dac91c5edc95cfb1e443f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB.
Could not build test google/cyan and intel/strago due to lack of UEFI
headers, OMG.
Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/12338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The function delay in uart8250mem.c is not enough for hudson. I guess
there are some problems in lapic_timer(). I uploaded a patch to gerrit
to show the way to enable UART feature.
http://review.coreboot.org/#/c/12343/4
Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to
enable this feature.
The UART is test at BIOS stage.
Since it is not a standart UART device, the windows internal UART driver
doesnt support it. I guess we need a driver to use it on windows.
Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11749
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I17660ce5429431e08476b7bba15e381636b64c7d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12053
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Change-Id: Iabd2e3e20b0e9719080f6bd7be2032c1749994dc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12056
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ifa0b61678fe362481891fc015cebe08485b66fc1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12047
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The coherent fabric on all Family 10h/15h devices supports
isochronous mode, which is required for IOMMU operation.
Add initial support for isochronous operation.
Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add options to control cache partitioning and overall memory
performance via nvram.
Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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