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2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23chromeos: vboot and chromeos dependency removal for sw write protect statePaul Kocialkowski
This removes the dependency on chromeos and vboot for the sw write protect state function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to both reflect this change and become consistent with the definition of get_write_protect_state that is already in use. Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-23google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOSPaul Kocialkowski
When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-23RISCV: modify arch_prog_run to handle payloads correctly.Ronald G. Minnich
Unlike the other stages, the payload requires virtual memory to be set up and also a privelege level change. Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/11699 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-22linking: link bootblock.elf with .data and .bss sections againAaron Durbin
Currently coreboot expects the loader to clear the bss section for all stages. i.e. stages don't clear their own bss. On ARM SoCs the BootROM would be responsible for this. To do that one needs to include the bss section data (all zeros) in the bootblock.bin file. This was previously being attempted by keeping the .bss info in the .data section because objcopy happened zero out non-file allocated data section data. Instead go back to linking bootblock with the bss section but mark the bss section as loadable allocatable data. That way it will be included in the binary properly when objcopy -O binary is emplyed. Also do the same for the data section in the case of no non-zero object values are in the data section. Without this change the trick of including .bss in .data was not working when there wasn't a non-zero value object in the data section. BUG=None BRANCH=None TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains the cleared bss. Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-22commonlib: add endian related accessor functionsAaron Durbin
This commit adds read/write functions for both big and little endian interpretations. Additionally there are variants that allow an offset to be provided into the source buffer. BUG=None TEST=Wrote test harness for functions. Also booted ARM QEMU through end of payload. Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11677 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-21cbfstool: don't use endian to fix BSD hostsAaron Durbin
endian.h lives in under sys on the BSDs. Replace htole32() with swab32(htonl(..)) as a proxy for little endian operations. Change-Id: I84a88f6882b6c8f14fb089e4b629e916386afe4d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11695 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-09-21cbfstool: make fmap search more strictPatrick Georgi
Since fmap doesn't come with a checksum, we resort to a number of heuristics to determine if a given location hosts an fmap (instead of another data structure that happens to store the fmap magic string at the right location). The version test is particularly effective against strings containing the magic (which either terminate with 0, or have some other ASCII data, but rarely a '\001' byte inside the string). Change-Id: Ic66eb0015c7ffdfe25e0054b7838445b8ba098e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-21cbfstool: add new add-master-header commandPatrick Georgi
The command adds a new cbfs file, fills in the CBFS meta data in cbfs master header format, then points the master header pointer (which resides at the last 4 bytes of the CBFS region) to the data area of the new file. This can leak some space in CBFS if an old-style CBFS with native master header gets the treatment, because a new header is created and pointed at. flashmap based images have no such header, and the attempt to create a second file with the (hardcoded) name will fail. Change-Id: I5bc7fbcb5962b35a95261f30f0c93008e760680d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11628 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-21ifdfake: allow "base+size" description of regionsPatrick Georgi
This is more in line with how fmd/fmap specify ranges. Change-Id: Iecf8250e84d6eb267711ded446909b21147f1a9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-19cbfstool: introduce new file typesPatrick Georgi
Let's move x86 style bootblocks (and later the others) and the master header into the CBFS structure. Prepare for this by adding file types. Change-Id: I1b4149c7f3b8564ee358a2c18ba91e6a7a6797da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11627 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-17libpayload: provide cbfs_file_find_attr()Patrick Georgi
cbfs_file_find_attr(file, tag) finds the first attribute of file with the given tag. Change-Id: I78ee3b996b4b086605244c5d7d57ef7e3fc1db47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11678 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-17cbfstool: Don't use fileno() to get file sizeStefan Reinauer
fileno() is a mess on some operating systems. Don't deliberately convert between FILE * and file handles. Change-Id: I5be62a731f928333ea2e5843d81f541453fdb396 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11636 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-17libpayload: allow compression at file header levelDaisuke Nojiri
Decompression is handled transparently within cbfs_get_file_content: const char *name = "foo.bmp"; void *dst = cbfs_get_file_content(media, name, type, NULL); To keep things consistent, a couple of API changes were necessary: - cbfs_get_file_content always returns a copy of the data, even for uncompressed files. It's the callers responsibility to free the memory. - same for cbfs_load_payload and cbfs_find_file. - cbfs_load_optionrom doesn't take a "dest" argument anymore but always returns a copy of the data, for compressed and uncompressed files. Like with cbfs_get_file_content, the caller is responsible to free it. It also decompresses based on extended file attributes instead of the cbfs_optionrom subheader that libpayload specified but that (AFAIK) nobody ever used, given that there's not even tooling for that. Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10938 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-17libpayload: rename cbfs variable from name to vardataDaisuke Nojiri
The dynamically sized region after struct cbfs_file doesn't contain only the file name anymore. Change-Id: I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11676 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17libpayload: bring in file attribute support from cbfstoolPatrick Georgi
This comes from cbfstool (GPL) into libpayload (BSD-l), but I could have just as well written it in libpayload first. Change-Id: I86baefe5c299125a4733fa20523efd5d06de7182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17broadwell: Switch to using common ACPI _SWS codeDuncan Laurie
Use the common ACPI _SWS code and provide a function to fill out the wake source data. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72 Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298168 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17braswell: Switch to using common ACPI _SWS codeDuncan Laurie
Switch braswell to use the common code for filling out the NVS data used by ACPI _SWS methods. This code was out of date on braswell so also update it to provide the \_GPE.SWS method. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-cyan coreboot Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0 Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17skylake: Use common ACPI _SWS codeDuncan Laurie
Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados/kunimitsu: remove the implementation of mainboard_add_dimm_inforobbie zhang
This is a follow-up patch to https://chromium-review.googlesource.com/#/c/286877, after fsp support is landed in v1.5. BUG=chrome-os-partner:42975 BRANCH=none TEST=execute "mosys memory spd print all" on glados and kunimitsu Change-Id: I949e287372b190affac36a0efde8a30402eecdc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298967 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529 Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados: 1-disable deep s3 in devicetree.cb 2-enable magic packet with "iw phy phy0 wowlan enable magic-packet" 3-powerd_dbus_suspend to go to S3 4-wake system with magic packet Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2 Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17Skylake: update C state latency and power numbersrobbie zhang
The values are taken from latest BWG as well fsp src. BRANCH=none BUG=chrome-os-partner:45208 TEST=Built and boot on kunimitsu Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164 Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b Original-Reviewed-on: https://chromium-review.googlesource.com/299480 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17drivers/intel/fsp1_1: split relocation code for tool useAaron Durbin
In order for easier consumption in userland tools split the FSP 1.1 relocation logic into a single file w/ an aptly named function name. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I49998b8621611c638375bc90884e80d0cd3bdf78 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc898e1c528df60683575d553d6194a1e8200afa Original-Change-Id: I736c0059d43f6d0be4fdb6e6f47cdb5c189a7ae8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298833 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17drivers/intel/fsp1_1: handle UEFI endiannessAaron Durbin
UEFI defines everything as little endian. Additionally the EDK II header files assume they are used on machines which are running UEFI -- thus little endian. This patch attempts to fix up all the possible endian violations when running on a big endian machine. This is for in preparation of using the FSP 1.1 code in userland for relocating FSP images. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I39f4de84688e48978a4650303b8af8345f44fd03 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c7eab9b7c10765355feffa3c3cac403275f9479 Original-Change-Id: I33a7661281307cf31ae33899d1a4eb6a2fbd01a1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298832 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11664 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17drivers/intel/fsp1_1: prepare relocation code for sharingAaron Durbin
In order to integrate fsp 1.1 relocation with cbfstool one needs to be able to supply the address to relocate the FSP image. Therefore, allow this by returning offset for return values. Note that exposed API has not changed. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Confirmed relocation values matched. Change-Id: I650a08ffb9caf7e0438a988cae9bec56dd31753c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53870b0df809418e9a09e7d380ad2399a09fb4fb Original-Change-Id: Ic2ec63681ed4e652e2624b40e132f95d1e5a0887 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298831 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/11663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17libpayload: usb: dwc2: check device connect state before enable channelYunzhi Li
If the device has already been disconnected then we shouldn't enable host channel to start any transfer, otherwise this channel goes into an odd state the channel is enabled but can not be disabled by set hcchar.chdis=1. So we need check the device connect status before enable channel. BRANCH=None BUG=chrome-os-partner:44534 TEST=None Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae3e690b2cd4a9ea8b5766ac873b0e00bf3a23de Original-Change-Id: Ib3ecf486649ca11b302144f9c00a5e88424e90fa Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298402 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-(cherry picked from commit ea96f947b5304fdde2e0991d23febaeba209dde1) Original-Reviewed-on: https://chromium-review.googlesource.com/299398 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4 Reviewed-on: http://review.coreboot.org/11662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17libpayload: usb: dwc2: fix hub hot-plug bugYunzhi Li
When disconnect is detected in dwc2_split_transfer() the split configuration registers should be cleared before return. BRANCH=None BUG=chrome-os-partner:44534 TEST=On Jerry, usb hot plug works with devices behind hubs Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37594d8b4490b6d393d19d17d8e497db7de8817d Original-Change-Id: Ie1eecec067305874513c6ceb95df4240dc393cd6 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295625 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-(cherry picked from commit d543e14cdc73bd549dd553c8d1d07672a1307981) Original-Reviewed-on: https://chromium-review.googlesource.com/299700 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib4604097743f2f9d763b29ee27f3bc1788a85a62 Reviewed-on: http://review.coreboot.org/11661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17linking: Repair special treatments for non-x86 bootblocksJulius Werner
Patch b2a62622b (linking: move romstage and bootblock to use program.ld) unified the linker scripts between different stages. Unfortunately it omitted several special cases from the old bootblock.ld script that are required for non-x86 environments. This patch expands program.ld to once again merge the .BSS into the program image for bootblocks (ensuring correct initialization by the external loader). It also revives the .id section (which adds a human-readable blurb of information to the top of an image) and fixes a problem with unintended automated section alignment. BRANCH=None BUG=None TEST=Jerry and Oak boot again. Change-Id: I54271b8b59a9c773d858d676cde0218cb7f20e74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6fddbc00963e363039634fa31a9b66254b6cf18f Original-Change-Id: I4d748056f1ab29a8e730f861879982bdf4c33eab Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/299413 Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17ifdtool: Properly set + decode flmstr regs for IFD v2Shawn Nematbakhsh
flmstr register bits have slightly different meaning for IFD v2. BUG=chrome-os-partner:45091, chrome-os-partner:43461 TEST=Run `ifdtool -d image.bin` on IFD v1 locked squawks image: Found Master Section FLMSTR1: 0x0a0b0000 (Host CPU/BIOS) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x0c0d0000 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR3: 0x08080118 (GbE) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: disabled Requester ID: 0x0118 Then, run `ifdtool -l image.bin` and verify newly locked image is identical. Next, run `ifdtool -l image.bin` on unlocked glados image. Verify that locked and unlocked regions are identical to above. Finally, burn glados image, run `flashrom -V`, and verify ME regions is locked and descriptor region is RO. BRANCH=None Change-Id: I8a65bdc5edd0d888138b88c1189f8badd1404b64 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11c434835a66a50ab2c0c01a084edc96cbe052da Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: I875dfce6f5cf57831714702872bfe636f8f953f4 Original-Reviewed-on: https://chromium-review.googlesource.com/298968 Original-Commit-Ready: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17t210: lp0_resume: Configure unused SDMMC1/3 pads for low power leakageYen Lin
In LP0 resume, a couple of SDMMCx pad settings need to be set to 0 to reduce power leakage. BUG=None BRANCH=None TEST=Tested on Smaug; able to suspend/resume >100 times Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f35a90a8af2180443db2c4be75d4566d0990de5 Original-Change-Id: Ifc946b0cea437ef0807cea0c11609d8e09387e8e Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298195 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Joseph Lo <josephl@nvidia.com> Original-(cherry picked from commit be3ac49a6bc4c9088d3799555d69c87c8ce1693c) Original-Reviewed-on: https://chromium-review.googlesource.com/298154 Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Change-Id: If5d5cebc89b8220480b3c72293a410e782eb437e Reviewed-on: http://review.coreboot.org/11656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-17intel/skylake: Create "RtcLock" Silicon UPD from corebootBarnali Sarkar
FSP should not lock CMOS unconditionally. coreboot sends Silicon UPD parameter "RtcLock" to FSP to take action on CMOS region locking/un-locking. This patch has CB generic code for creating the Silicon UPD paramater. BUG=chrome-os-partner:44484 BRANCH=none TEST=Build and booted in kunimitsu, tested using below command- When DIsabled RtcLock from devicetree in coreboot, booted to kernel and run following commands - >> crossystem fw_result=success >> crossystem | grep fw_result It should reflect the value that is set. Here, success. If ENabled RtcLock from Coreboot devicetree, The same commands will fail to update the fw_result status from crossystem utility. CQ-DEPEND=CL:*229144 Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297980 Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17vbnv: check alignment of nvram in advanceDaisuke Nojiri
Currently, erase operation only works if the region is sector-aligned. These asserts ensure we can erase the region when it's all used up. Erase operation can be updated to handle unaligned erases by read, update, write-back cycle. However, these asserts will still remain useful in case the adjacent region contains critical data and mis-updating it can cause a critical failure. Additionaly we should write a FAFT test but it's more reliable to catch it here since FAFT can fail in many ways. BUG=none BRANCH=master TEST=tested on samus using misaligned nvram region Change-Id: I3add4671ed354d9763e21bf96616c8aeca0cb777 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc001a4d3446cf96b76367dde492c3453aa948c6 Original-Change-Id: Ib4df8f620bf7531b345364fa4c3e274aba09f677 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297801 Reviewed-on: http://review.coreboot.org/11654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298234 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655 Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298233 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17intel/common: Add common code for filling out ACPI _SWSDuncan Laurie
Add common code for filling out the NVS fields that are used by the ACPI _SWS methods. The SOC must provide a function to fill out the wake source data since the specific data inputs vary by platform. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I4f3511adcc89a9be5d97a7442055c227a38c5f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cee5fa176c16ca44712bce8f3c8045daa5f07339 Original-Change-Id: I16f446ef67777acb57223a84d38062be9f43fcb9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298167 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11646 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17cbfstool: deduplicate MakefilesPatrick Georgi
There's no need to maintain two lists of dependencies that need to be changed every. single. time. Change-Id: I26bb8c884e98afe74fd9df11464bcf88e130cd92 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17cbfstool: actually use no-ms-bitfields flag on mingwPatrick Georgi
It was added to an unused variable. Change-Id: I869ffdda7e04b5c615931473c760d66b803fb98b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-16riscv-virtual-memory: move page tables into virtual address spaceThaminda Edirisooriya
If we use a linux payload/any payload that wants to manage virtual memory, and the payload is a supervisor (thus requiring virtual addressing before being started), we need to make sure that the page table is mapped into the virtual address space. Move the start address of the tables so the payload can manage virtual memory. Change-Id: I1d99e46f38a38a163fb1c7c517b1abca80cde0dc Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11621 Tested-by: build bot (Jenkins)
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Add utility code to qemu-riscv, but emulator itself has yet to be updated to new ISA and as such should not be used. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Fixed whitespace issues in spike_util.c Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-16kunimitsu: Enable ALS connected to ECDuncan Laurie
Kunimitsu has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2 Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298252 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16glados: Enable ALS connected to ECDuncan Laurie
Glados has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=test ALS functionality on glados P2 board Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054 Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16kunimitsu: Disable Deep S3 on kunimitsu platformSubrata Banik
This patch will reset Deep S3 flag, hence S3 will work. BUG=chrome-os-partner:40635 BRANCH=None TEST=Build and Boot Kunimitsu and verify S3 is working. Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5 Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16Move final Intel chipsets with ME to intel/common/firmwareMartin Roth
This switches the final 4 Intel platforms that use ME firmware from using code specific to the platform to the common IFD Kconfig and Makefile. braswell, broadwell, bd82x6x (cougar point & panther point) and ibexpeak Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10876 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-16cbfstool: remove locate commandAaron Durbin
The locate command was previously being used for x86 romstage linking as well as alignment handling of files. The add command already supports alignment so there's no more users of the locate command. Remove the command as well as the '-T' (top-aligned) option. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Noted microcode being directly added. Change-Id: I3b6647bd4cac04a113ab3592f345281fbcd681af Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16x86: remove double link step for romstageAaron Durbin
Now that cbfstool supports XIP for romstage utilize it. This removes the double link steps with the cbfstool locate and add-stage sandwich. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11670 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16cbfstool: add --xip support to add-stage for x86Aaron Durbin
Instead of going through the locate then add-stage dance while linking romstage twice allow for adding romstage with --xip flags to perform the relocation while adding it into CBFS. The -P (page-size) and -a (alignment) parameters were added as well so one could specify the necessary parameters for x86 romstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Change-Id: I585619886f257e35f00961a1574009a51c28ff2b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16cbfstool: provide metadata size to cbfs_locate_entry()Aaron Durbin
The cbfs_locate_entry() function had a hack in there which assumed a struct cbfs_stage data was being added in addition to the struct cbfs_file and name. Move that logic out to the callers while still maintaining the logic for consistency. The only impacted commands cbfs_add and cbfs_locate, but those are using the default 'always adding struct cbfs_stage' in addition to cbfs_file + name. Eventually those should be removed when cbfs_locate is removed as cbfs_add has no smarts related to the cbfs file type provided. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Change-Id: I2771116ea1ff439ea53b8886e1f33e0e637a79d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16cbfstool: expose rmodule logicAaron Durbin
In order to allow cbfstool to add XIP romstage on x86 without doing the 'cbfstool locate', relink, then 'cbfstool add' dance expose the core logic and of rmodule including proving an optional filter. The filter will be used for ignoring relocations to the .car.global region. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Change-Id: I192ae2e2f2e727d3183d32fd3eef8b64aacd92f4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11598 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 19:24:35 +0000