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2020-07-24superio/common: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing a pointer that might be "NULL" when calling report_resource_stored. Add sanity check for dev to prevent NULL pointer dereference. Found-by: Coverity CID 1419488 Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I03efad87ba761e914b47e3294c646335cfbaed24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-24soc/amd/picasso/fsp_params: add missing newline between functionsFelix Held
Change-Id: If5d798a410f092e0ce99c16c84809b6b2e30cc2e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43779 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso/fsp_params: add asserts for descriptor countFelix Held
With the updated FSP UPD headers there are enough DXIO descriptor slots in the UPD, so we can now add asserts to make sure that the mainboard doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This is part of the DXIO/DDI descriptor handling cleanup. BUG=b:158695393 Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24vc/amd/fsp/picasso: update UPD headerFelix Held
A new version of UPD headers generated from the FSP tree. This adds UPDs for downcoring and increases the number of DXIO descriptor slots. BUG=b:161152720 TEST=SATA on Mandolin works now. Cq-Depend: chrome-internal:3175393 Change-Id: I1e27597e22af4df65d206a38b67c4920298b30b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43659 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/ocp/tiogapass: Use macro to configure IIOMaxim Polyakov
Use macros to configure each of the IIO ports instead of an array of some unknown parameters. This will clean up the code and make it easier to read. Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical. Change-Id: I2911992435a6c93624525426d56212f821abb866 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24nb/intel/sandybridge: Remove unnecessary `struct sys_info`Angel Pons
It was only used in one function, but its value was never read. Drop it. Change-Id: Ib511352d51d4452d666640d0f52810b06c8d61ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24nb/intel/ironlake: Move southbridge code to ibexpeakAngel Pons
There's no need to set up the southbridge in the northbridge code. Change-Id: I0f80c92aca885812c27a8803c2745844d8dfb939 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24sb/intel/*: Delete invalid commentAngel Pons
Looks like these comments were moved without checking them. They are no longer correct nor useful, so kill them with fire. Change-Id: I3de04b8c03f7c511376dec922a60958ffc3bf6a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24mb/ocp/deltalake: Send OEM IPMI command for CMOS clear on RTC failureJingle Hsu
When RTC failure is detected, send IPMI OEM command to issue CMOS clear. This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS clear command by resetting RTC data, erasing RW_VPD (TODO) and add a SEL, then reboot the system. Tested=on OCP Delta Lake, after removing RTC battery we can see the above flow can be executed correctly. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/ocp/tiogapass: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU 2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN. Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/google/octopus/variants/garg: update Garfour SKU IDTony Huang
SKUID 51 - Garfour EVT (non-touch, TypeA DB) 52 - Garfour DVT (touch, HDMI DB) BUG=b:161554087 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I3cb17c2b665c303da210817a531c869c6324b249 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com>
2020-07-23mb/google/zork: Don't expose reset GPIO for touchscreen to OSRaul E Rangel
The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF method to the kernel. These are contradictory. The ownership of the GPIO should be mutually exclusive between either the OS or the FW. Since we have two methods exposed this causes the OS to reset the TS twice. Once using the _ON method, and once using the GPIO. Additionally the _ON method is waiting for 20ms after reset while the OS driver uses a 50ms delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the OS driver is adding additional padding. The reference design has a 32ms rise time on the reset line. So without this patch, the OS tries to reset the TS using the _ON method and it waits for 20ms. This is not enough time for the reset line to reach high, let alone account for the FW ready time. The OS driver then tries to reset the device by toggling the GPIO. It waits 50ms which is still 2ms less than required. This CL removes the GPIO from being exported in the _CRS so the OS driver won't try and reset the device. It also increases the reset delay by 32ms to account for the rise time. This isn't a complete fix. I think that the slow rise time is causing some kind of metastability in the TS reset hardware. Using a script to bind and unbind the TS driver, the TS device becomes unresponsive after ~200 iterations. The only way to reset the device is to power cycle. The TS power is also not currently controlled by the power resource. This means that we have no guarantee over when the reset line is toggled. This will lead to issues while spending and resuming. BUG=b:160854397 TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+ times. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-23mb/google/zork/variants/dalboz: Use HS200 for eMMCEric Peers
Earlier versions of Dalboz did not correctly handle HS400. One fix was to add stitching vias, but these boards did not have them. b/156539551 Another possible fix is to add tuning parameters including drive strength, but that is still a WIP. b/158959725 This should correct OS load failures in the meantime by running the bus slower. BUG=b:158845662 TEST=build, flash, boot sku 0x5a80000c to OS BRANCH=None Signed-off-by: Eric Peers <epeers@google.com> Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23zork: Create dirinboz variantKevin Chiu
Create the dirinboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:161579679 BRANCH=master TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_DIRINBOZ Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-07-23mb/google/arcada: Enable bayhub 720 on ArcadaMark Hsieh
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree. BUG=b:157971972 BRANCH=sarien TEST=local build and boot from SATA/PCIe-eMMC storage successfully Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/sarien: Enable bayhub 720 on SarienIvy Jian
Add PCIe-eMMC bridge bayhub 720 on Sarien. BUG=b:157971972 BRANCH=sarien TEST=local build and boot from storage successfully Change-Id: I28f40a420d51f476487655548f386cfbdc2e5329 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-07-23mb/google/dedede/var/waddledoo: Configure stop delay for SiS TSKarthikeyan Ramasubramanian
Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at the same time. Add a delay of 100 ms after disabling the stop GPIO. This will ensure the required delay is inserted for both reset and stop disable GPIOs simultaneously. BUG=b:152936541 TEST=Build and boot the waddledoo mainboard. Ensure that the SiS Touchscreen is functional. Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede/var/drawcia: Generate SPD ID for supported partsKarthikeyan Ramasubramanian
Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR BUG=None TEST=Build the drawcia board. Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/zork: Fix Goodix touchscreen ACPI nodeFurquan Shaikh
This change does the following: a. USI_REPORT_EN is no longer set to high in coreboot. Instead GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this pad as required. b. Appropriate delays are added for power-down sequencing: - Delay after REPORT_EN is disabled - 1ms - Delay after RESET is asserted - 1ms BUG=b:159501288 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork/var/morphius: Change hid and desc for Goodix touchscreenFurquan Shaikh
Morphius uses Goodix touchscreen and not G2 touchscreen. This change updates hid and desc properties in devicetree accordingly. BUG=b:159501288 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I2527fa5409bb127ac225c6fb2a5f1bc24895f6cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Drop TODO for GPIO_91Furquan Shaikh
GPIO_91 is added to ACPI using the device tree entry for codec. So, this change drops the TODO from GPIO table. Change-Id: I9c2e91465ab554126531f8512028360ae5fb316d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Configure all pads in ramstage for dalboz referenceFurquan Shaikh
This change configures all missing pads in ramstage for dalboz reference. This ensures that the state of all pads is set correctly for the payload/OS. Also, all the pads for the platform are configured in baseboard gpio table in ramstage to ensure that variants can override any pads if required. BUG=b:154351731 Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Configure all pads in ramstage for trembyle referenceFurquan Shaikh
This change configures all missing pads in ramstage for trembyle reference. This ensures that the state of all pads is set correctly for the payload/OS. Also, all the pads for the platform are configured in baseboard gpio table in ramstage to ensure that variants can override any pads if required. BUG=b:154351731 Change-Id: Idd827b6a4f995546493596f22249f8699bdf526b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/zork: Remove unnecessary PULL_UP from early_gpio_tableFurquan Shaikh
This change drops PULL_UP configured on pads in early_gpio table since these pads have external pulls. BUG=b:154351731 Change-Id: Id270e7b4f83dfa942655f513776a3b1c15c9678d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23soc/amd/common/gpio: Fix definition of GPIO_INT_ENABLE_STATUS_DELIVERYFurquan Shaikh
This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY` to use `GPIO_INT_ENABLE_DELIVERY` instead of `GPIO_INT_ENABLE_STATUS_DELIVERY`. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64d912200779875cf121cec4476fd39de74c0223 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23vc/amd/fsp/picasso: add logical to lane number in port descriptor structFelix Held
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23mb/google/kukui: Add new configs 'esche' and 'burnet'Kevin Chiu
new boards introduced to Kukui family. esche: clamshell burnet: 360 convertible BUG=b:161768221 BRANCH=master TEST=emerge-jacuzzi coreboot Change-Id: I2245c34533549bb94c58938fee5778b8a03e2767 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-23mb/prodrive/hermes: Update VBT fileChristian Walter
Update .vbt file to support two DP outputs. Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23MAINTAINERS: Add Jeremy Soller for ec/system76 and mb/system76Jeremy Soller
I currently maintain System76 coreboot support. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I4240618c9d9846c3b9e30db4d5ac725e1ca2a09c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43674 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23ec/system76_ec: add support for System76 ECJeremy Soller
This adds ACPI code for System76 EC and converts system76/lemp9 to use EC_SYSTEM76_EC. Tested on system76/lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-23mb/ocp/deltalake: Add ipmi POST start command in romstageTimChu
Add function to send POST start command to BMC. This function is used in romstage and the POST end command will be sent in u-root. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1: ipmid: POST Start Event for Payload#2 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23mb/ocp/deltalake: Implement SMBIOS type 9 -- system slots by SKUMorgan Jang
Create SMBIOS type 9 by getting PCIe config from BMC. TEST=Check SMBIOS type 9 is created correctly on different SKUs Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-23soc/intel/xeon_sp/cpx: display SystemMemoryMapHob fieldsJonathan Zhang
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things. It is a fairly large structure, so the pointer to the data instead of the structure itself, is included in the HOB. Use pointer to SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body. Adjust the structure definition to match with CPX-SP ww28 release. Display more fields to ensure the structure definition is correct. TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob to make sure they are correct: 0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID ================== MEMORY MAP HOB DATA ================== hob: 0x777f7000, structure size: 0x6c88 lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0 memSize: 0x600, memFreq: 0xb76 NumChPerMC: 3 SystemMemoryMapElement Entries: 2, entry size: 16 memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1 memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1 BiosFisVersion: 0x0 MmiohBase: 0x80000 0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23libpayload: cbgfx: Add draw_line()Yu-Ping Wu
Add a function draw_line() to draw either a horizontal or vertical line segment. Theoretically a horizontal line can also be drawn by calling draw_rounded_box() with dim_rel.x being the line length and dim_rel.y being the line width. However, due to the truncation in integer division when converting relative coordinates to absolute ones, this will potentially produce inconsistent line widths, depending on the value of pos_rel.y. It is guaranteed that draw_line() will produce consistent line widths, regardless of the position of the line. Also, when the thickness argument is zero, this function is able to draw a line with 1-pixel width, which is not achievable by draw_rounded_box(). BRANCH=puff BUG=b:146399181, b:161424726 TEST=emerge-puff libpayload Change-Id: I2d50414c4bfed343516197da9bb50791c89ba4c2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-07-23mb/intel/jasperlake_rvp: Enable CSE Firmware Lite SKU for JSLRVPKrishna Prasad Bhat
This patch enables CSE Lite SKU for jasperlake rvp. BUG=b:160201335 BRANCH=None TEST=Build and boot jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I60039ffb1f24cf98f55e83d8c8649745598aa43a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40571 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvpKrishna Prasad Bhat
This patch enables the SkipCpuReplacementCheck config for jasperlake rvp to avoid the forced MRC training with the soldered down SOC. BUG=b:160201335 BRANCH=None TEST=Build and verify on jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/google/dedede: Enable the CSE Lite SKU for dededeV Sowmya
This patch enables the CSE Lite SKU for the dedede baseboard. BUG=b:160201335 TEST=Build and boot waddledoo with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23mb/google/dedede: Skip the CPU replacement check for dededeV Sowmya
This patches enables the SkipCpuReplacementCheck config for the dedede baseboard to avoid the forced MRC training for all its variants with the soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddledoo. Cq-Depend: chrome-internal:3142530 Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23soc/intel/jasperlake: Add the SkipCpuReplacementCheck configurationV Sowmya
Add SkipCpuReplacementCheck config to control the FSPM UPD used for skipping the CPU replacementment check to avoid the forced MRC training for the platforms with soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddleddo. Cq-Depend: chrome-internal:3142530 Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-22sb/intel/i82801jx/hdaudio.c: Rename to `azalia.c`Angel Pons
Other Intel southbridges use this name for the HD audio codec. Change-Id: Ic96797e6c2028f082130211bb5f4270391f866c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22sb/intel/i82801ix/hdaudio.c: Rename to `azalia.c`Angel Pons
Other Intel southbridges use this name for the HD audio codec. Change-Id: I50dbf0a079944b7fa6cfd6622c0626bc9139af85 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22sb/intel/i82801ix/sata.c: Use `probe_resource`Angel Pons
It is impossible for `find_resource` to return NULL, it dies instead. Change-Id: If8e26f768383e741100e3690322db3dabeec1922 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)Tim Wawrzynczak
A recent Coverity scan found an issue with the way the EC_HOST_EVENT_MASK macro was being used. It was being passed values between 0 and 63, but since it is doing basically (1ULL << (value - 1)), this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd bit of the mask. This is fixed by incrementing the start and end conditions of the loop by 1, so the event mask ranges from bits 0 to 63, instead of -1 to 62. Found-by: Coverity CID 1430218 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-22soc/intel/jasperlake: Move tco_configure to bootblockTim Wawrzynczak
Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on jasperlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22soc/intel/cannonlake: Move tco_configure to bootblockTim Wawrzynczak
Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on cannonlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22mb/google/zork: Modify Woomax variantKane Chen
Update Woomax configuration including GPIO, memory SPD table, I2C devices and USB type C. BUG=b:158343602 BRANCH=None TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-22nb/intel/i945: Put names to northbridge PCI devicesAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22mainboard/amd/mandolin: describe where the two HDA codecs resideFelix Held
Change-Id: I99b062e4ce1cf862ea03b0edb6ea843df5f8f2b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22mb/ocp/deltalake: Unset POWER_STATE_DEFAULT_ON_AFTER_FAILURETim Chu
Change PCH power policy. Set default of POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power state to S5 when power is reapplied after power failure. TEST=Base on CB:42289, CB:43338 and build for Deltalake. The following Kconfig options must be selected: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and check the last bit of GEN_PMCON_B is set to 1 through ITP with command: pch.pm_dump Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 20:37:09 +0000