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AgeCommit message (Expand)Author
2015-04-22Makefile: Avoid duplicate class suffixes in $(call src-to-obj)Julius Werner
2015-04-22qualcomm/ipq806x: report versions of RPM and DDR init componentsVadim Bendebury
2015-04-22qualcomm/ipq806x: add board id value for SP5Vadim Bendebury
2015-04-22google/urara: retrieve board ID from a CBFS fileVadim Bendebury
2015-04-22broadcom/cygnus: add timestamps in pre-ram stagesDaisuke Nojiri
2015-04-22google/purin: add DMA coherent regionDaisuke Nojiri
2015-04-22broadcom/cygnus: Initialize dram in romstage.Icarus Chau
2015-04-21broadcom/cygnus: Fix missing writel->write32 transformationPatrick Georgi
2015-04-21libpayload: add timer driver for cygnusDaisuke Nojiri
2015-04-21cygnus: add QSPI driverCorneliu Doban
2015-04-21veyron: add new SDRAM configuration with ram-code 1101bZhengShunQian
2015-04-21pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu
2015-04-21pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu
2015-04-21pistachio: clean DDR2 initialization codeIonela Voinescu
2015-04-21cygnus: enable serial driver for depthchargeDaisuke Nojiri
2015-04-21storm: print uber-sbl informationVadim Bendebury
2015-04-21armv7: preserve bootblock invocation parameterVadim Bendebury
2015-04-21ipq808x: add uber sbl parameter definitionsVadim Bendebury
2015-04-21urara: I2C clock and MFIO setup function for all interfacesIonela Voinescu
2015-04-21pistachio: add clock setup for all I2C interfacesIonela Voinescu
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
2015-04-21arm(64): Manually clean up the mess left by write32() transitionJulius Werner
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
2015-04-21arm(64): Change write32() argument order to match x86Julius Werner
2015-04-21arm(64): Replace write32() and friends with writel()Julius Werner
2015-04-21romstage_handoff: Fix for changing CBMEM structureDuncan Laurie
2015-04-21veyron_{brain,danger}: Specify vboot romstage and ramstage indicesDavid Hendricks
2015-04-21rk3288: disable rk808 DCDC_UV_ACT_REG restart converter functionhuang lin
2015-04-21veyron: The ODT function is disabled for LPDDR3jinkun.hong
2015-04-21veyron: Sync up SDRAM configurationsJulius Werner
2015-04-21rockchip: configure lpddr odt properlyDerek Basehore
2015-04-21cbfs: Print absolute offsets of loaded filesVadim Bendebury
2015-04-21veyron_jerry: support K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3jinkun.hong
2015-04-21x86: Allow builds without ACPI tablesLee Leahy
2015-04-21ipq806x: i2c: stop transfer as soon as an error is reportedSourabh Banerjee
2015-04-21ipq806x: i2c: write function fixed to avoid spurious successSourabh Banerjee
2015-04-21libpayload: mips: Do not set C0_EBase_WGAndrew Bresticker
2015-04-21libpayload: mips: Add macros to convert to/from KSEG{0,1} addressesAndrew Bresticker
2015-04-21arch/mips: simplify cache operationsIonela Voinescu
2015-04-21rk3288: support single channel ddrjinkun.hong
2015-04-21libpayload: mips: Use KSEG1 to access DMA-coherent memoryAndrew Bresticker
2015-04-21libpayload: mips: Set BASE_ADDRESS to 0Andrew Bresticker
2015-04-21urara: Identity map DRAM/SRAMAndrew Bresticker
2015-04-21mips: Allow memory to be identity mapped in the TLBAndrew Bresticker
2015-04-21broadwell: Clear USB3.0 PORTSC status bits in sleep_prepare.Todd Broch
2015-04-21broadwell: indent xhci codePatrick Georgi
2015-04-21broadwell: Skip pre-graphics delay in resume pathDuncan Laurie
2015-04-21broadwell: Implement Recovery ButtonRyan Lin
2015-04-21Arrange CBMEM table entries' IDs alphanumericallyVadim Bendebury
2015-04-21urara: add config of SPI bus and correct selection of winbond flashIonela Voinescu
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