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2011-12-31White space and coding style fixes.Nils Jacobs
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736 Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/511 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-26Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.Marc Jones
I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location. Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/487 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-26trivial:change the value type of POST_PORT in Kconfig from int to hexVikram Narayanan
trivial change in src/console/Kconfig Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/505 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Sconfig: parse Kconfig options from devicetree.cbKyösti Mälkki
Mainboard and chip Kconfig files have several build options that are redundant with information in devicetree.cb. This patch enables sconfig to auto-generate equivalent configuration. sconfig -s Generates mainboard's static.c file, as before. sconfig -b This operation creates mainboard's bootblock init code. By default, for every chip listed in mainboard/devicetree.cb, if there is a chip/bootblock.c file, the init function is called. A mainboard/bootblock.c file can be added to override default behaviour. sconfig -k This operation generates select -options for component paths. Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Only BSP CPU writes CMOS in bootblock codeKyösti Mälkki
CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. AP CPUs should always select the same romstage prefix as BSP CPU. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/446 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24libpayload: remove uhci_reg_maskXPatrick Georgi
Not that good an idea to start with. Coccinelle patch: @@ @@ -void ( -uhci_reg_mask8 | -uhci_reg_mask16 | -uhci_reg_mask32 ) - (...) { ... } @@ @@ -void ( -uhci_reg_mask8 | -uhci_reg_mask16 | -uhci_reg_mask32 ) - (...); @@ expression ctrl, reg, ormask; @@ -uhci_reg_mask32 (ctrl, reg, ~0, ormask) +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask) @@ expression ctrl, reg, ormask; @@ -uhci_reg_mask16 (ctrl, reg, ~0, ormask) +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask) @@ expression ctrl, reg, ormask; @@ -uhci_reg_mask8 (ctrl, reg, ~0, ormask) +uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask) @@ expression ctrl, reg, andmask; @@ -uhci_reg_mask32 (ctrl, reg, andmask, 0) +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask) @@ expression ctrl, reg, andmask; @@ -uhci_reg_mask16 (ctrl, reg, andmask, 0) +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask) @@ expression ctrl, reg, andmask; @@ -uhci_reg_mask16 (ctrl, reg, andmask, 0) +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask) Change-Id: Id0eb8327293831e54249d43fd06d50963c793699 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/477 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-24Let lib_get_sysinfo() pass through the success of get_coreboot_info()Philip Prindeville
The return status of get_coreboot_info() might be handy to a platform driver calling lib_get_sysinfo() to test for the presence of coreboot. Change-Id: I0176c93ee92c9dff733112026ee50f2ca797bdff Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> Reviewed-on: http://review.coreboot.org/503 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Fix missing cast back to void *Philip Prindeville
MEM_RANGE_PTR() also needs to return a pointer to untyped memory. Change-Id: I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1 Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> Reviewed-on: http://review.coreboot.org/500 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Fix missing VM mappingPhilip Prindeville
When processing FORWARD records, we weren't accounting for the pointer being in the physical address space and not the virtual space instead. Change-Id: I35ef637fbec7886d4cfeac5fd650a17eae8d555a Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> Reviewed-on: http://review.coreboot.org/499 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Use void pointers for untyped memoryPhilip Prindeville
To avoid unnecessary casts, we can use untyped pointers when accessing individual records. Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3 Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> Reviewed-on: http://review.coreboot.org/498 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Use convenience function to checksumPhilip Prindeville
That coreboot uses the IP checksum is an artifact, not a deliberate requirement to be compatible with the Internet Protocole suite. Use a wrapper to abstract the computation of coreboot's checksum. Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370 Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> Reviewed-on: http://review.coreboot.org/497 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-24Replace UNPACK_CB64 macro with inlinePhilip Prindeville
Having submitted a module based on coreboot to LKML for acceptance, it was requested that fewer macros and more inlines be used (because of their superior type-checking when performing pointer casts, etc). This is the first of several changes to make the relevant parts of coreboot comply to linux code standards. Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com> Reviewed-on: http://review.coreboot.org/495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-22south_station: Enable GNB hd audioKerry Sheh
Enable HD audio over HDMI. Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed. Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/450 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-21Add RS780 defaut graphics ID to AMD Mahogany mainboard.Marc Jones
Added the default ID to the mainboard Kconfig. Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/488 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2011-12-21Respect linker orderChristian Ruppert
Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed through a compiler specs file. A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo $(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the libraries/dependencies must be passed *after* the objects. For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0 Signed-off-by: Christian Ruppert <idl0r@qasl.de> Reviewed-on: http://review.coreboot.org/494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-21kbd: wait longer for self-test on keyboard resetMathias Krause
Some keyboards take pretty long to respond to a reset command, some even delay the ACK to the command. To make the keyboard driver more robust, increase the timeout for this special command. Also do an interface test after the self-test to ensure the keyboard is functioning properly. Another point is to reenable the keyboard *after* the scancode was set, not before. We also set the system bit when enabling the keyboard because this seems to be what older operating systems do expect. One of the problematic keyboards, which will work with this patch applied, is the DELL RT7D20. Without the patch an overly optimistic operating system, read Linux 2.4, will not recognise the keyboard because coreboot didn't fully initialize it. Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Reviewed-on: http://review.coreboot.org/486 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-21Persimmon audio codec verb patch.Marc Jones
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb data is not required for mainboards that use G-Series HDMI. It is also a setting the may be boards specific. This fixes issues with Windows audio on Persimmon. Change-Id: I067506871e92078d122cf79872363d8937d47e50 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/490 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-15.gitignore util/crossgcc/build-* and unpacked source directoriesPeter Stuge
Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/484 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-14Lenovo X60/T60: add first_battery settingSven Schnelle
The EC allows to select the order in which batteries are (dis)charged. Make this setting available to the user. Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/475 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14asus k8v-x: explicitly set RAM and bus voltagesFlorian Zumbiehl
Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/482 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-xFlorian Zumbiehl
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/481 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-13Fix console output in real mode int10 implementation.Stefan Reinauer
Checking RBIL, int10 AH=0x10 does never output a character. The two output functions are AH=0x09 and AH=0x0e. Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/483 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-13libpayload: add set_option() functionPatrick Georgi
It allows to change CMOS values from payloads Change-Id: I4872fc27476923adafe13504126235b92b30de85 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/445 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-13Fix CMOS handling for non-USE_OPTION_TABLE configurationPatrick Georgi
The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols, which fail without an option table (as no option_table.h defines them). Discard them by using a macro instead of a static inline function. Change-Id: I8d001f971681277a344b6788725746491546b607 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/442 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-13Use MMCONF for all AMD family 10 CPUs.Marc Jones
This fixes problems in AP init when multiple APs are trying to access PCI config space. All Fam10 CPUs setup and support MMCONF. Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/455 Tested-by: build bot (Jenkins) Reviewed-by: Alec Ari <neotheuser@ymail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-08Change DSDT Table ID for M4A785T-M boardAlec Ari
Change the DSDT Table ID for M4A785T-M from M4A785-M to M4A785T-M. This fixes a small copypasta. This is an updated patch set. Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-08Fix ldscript for bootblock .rom sectionKyösti Mälkki
Allocation size for the section was miscalculated, so the section did not honour its upper-bound address. Also align the section start to 4 bytes, so it starts with code instead of pad bytes. Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/453 Tested-by: build bot (Jenkins) Reviewed-by: Alec Ari <neotheuser@ymail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-06Fix AMD 8132 and 8151 southbridge buildsKyösti Mälkki
Untested, changes ramstage build for boards: supermicro/h8qme_fam10 amd/serengeti_cheetah amd/serengeti_cheetah_fam10 AMD 8132 was not built for any mainboard due to a typo. AMD Serengeti Cheetah: Chip 8151 is referenced in devicetree.cb but was not built. AMD Serengeti Cheetah Family10: There are indications the board has 8151, but it is not listed in the devicetree.cb. The 8151 chip is not added in the build. Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/471 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-05RS780: print the vgainfoDenis 'GNUtoo' Carikli
With this commit the vgainfo is printed and looks like that on the serial console: vgainfo: ulBootUpEngineClock:50000 ulBootUpUMAClock:66700 ulBootUpSidePortClock:0 ulMinSidePortClock:0 ulSystemConfig:0 ulBootUpReqDisplayVector:0 ulOtherDisplayMisc:0 ulDDISlot1Config:0 ulDDISlot2Config:0 ucMemoryType:0 ucUMAChannelNumber:1 ucDockingPinBit:0 ucDockingPinPolarity:0 ulDockingPinCFGInfo:0 ulCPUCapInfo: 2 usNumberOfCyclesInPeriod:0 usMaxNBVoltage:0 usMinNBVoltage:0 usBootUpNBVoltage:0 ulHTLinkFreq:20000 usMinHTLinkWidth:8 usMaxHTLinkWidth:8 usUMASyncStartDelay:100 usUMADataReturnTime:300 usLinkStatusZeroTime:600 ulHighVoltageHTLinkFreq:20000 ulLowVoltageHTLinkFreq:20000 usMaxUpStreamHTLinkWidth:8 usMaxDownStreamHTLinkWidth:8 usMinUpStreamHTLinkWidth:8 usMinDownStreamHTLinkWidth:8 Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-03adding support for the Asus K8V-XFlorian Zumbiehl
This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/390 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-12-03Fix Asus A8V-E SE DIMM slot mappingRudolf Marek
Fix the DIMM mappings, channel 0 is "B" on board, and secondary channel is on 0x51,0x53 Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/449 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02make GPIOs and misc configurable via devicetreeFlorian Zumbiehl
Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/387 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02make INT[EFGH]# of vt8237 configurable as gpio via devicetreeFlorian Zumbiehl
Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/386 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02copied asus a8v-e_se to k8v-xFlorian Zumbiehl
Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/389 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02some black magic for initializing the old version of the k8t800Florian Zumbiehl
Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/388 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02implement usb2 termination and dpll delay setting for vt8237rFlorian Zumbiehl
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/385 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02i3100: Add HAVE_HARD_RESETSven Schnelle
and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Mirror Fix coreinfo usage of cb_infoQingPei Wang
fix cb_info.serial.ioport to cb_info.serial.baseaddr Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/441 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02M4A785T-M: fix ACPI's P-States TableDenis 'GNUtoo' Carikli
Without that fix the linux kernel cannot change the frequency of the CPUs with cpufreq. Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Add ASUS M4A785T-M mainboard supportDenis 'GNUtoo' Carikli
This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init This change was tested with the Trisquel 5.0 GNU/Linux distribution which uses the linux-libre version 2.6.38-12-generic The mainboard boots fine, however some special care is required for the onboard sound CODEC, and the onboard video chip: * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue is the same than the ASUS M4A785-M mainboard: It causes a flood of interupts which prevents booting * The internal video chip currently requires pci=nocrs, else the graphics are frozen as soon as the radeon module loads, and dmesg would print the following(the card only has 256M, and the mainboard was equiped with 2G of RAM): [ 3.674762] [drm] radeon: 3584M of VRAM memory ready [ 3.679863] [drm] radeon: 512M of GTT memory ready. instead of : [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. * The screen(both VGA and HDMI) flickers at high resolution * Sometimes the computer freeze while changing the resolution (even the serial console stops responding) The following peripherals were tested: * The ath9k PCI wireless card was tested * The SATA hard disk works fine * the USB keyboard and mouse work fine * htop see 2 cores * serial port works under coreboot and GNU/Linux * power off and reboot works CPU frequency cannot be changed yet, this is addressed in a new commit. More detail are available here: http://www.coreboot.org/ASUS_M4A785T-M dmesg is available here: http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html The mailing list thread on the graphic problem is here: http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Remove obsolete TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-01X60/T60: reset baudrate loglevel to sane valuesSven Schnelle
Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/459 Tested-by: build bot (Jenkins)
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
Following files were no longer used in the build and are deleted: src/arch/x86/init/entry.S src/arch/x86/init/ldscript.ld Also fix ugly whitespace in code copyrights and comments. Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-24vt8237: add support for setting the power state after loss of powerFlorian Zumbiehl
Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/437 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-23k8 raminit: fix bug, improve clock selection, add clock limit for sock754Florian Zumbiehl
in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/377 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-22implement hwmon fan divisor setting for w83697hfFlorian Zumbiehl
Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/384 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-11-22k8 raminit: add workaround for erratum #181 on non-fam-fFlorian Zumbiehl
Disable DRAM controller on non-fam-f CPUs not using fam-f register layout. Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/448 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
Relocate early post_code() so it gets executed and does not corrupt BIST at %eax. Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:08:13 +0000