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2016-05-06soc/intel/apollolake: Correct PCI write size in romstageFurquan Shaikh
1. PCI command reg write should be 16-bit. 2. HPTC reg write should be 8-bit. Also, use macros instead of hard-coded values. Currently, the macros are defined in romstage.c, but if more P2SB macros are added, it would be good to move them to a separate header file. Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14613 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-05-05build system: create fmap for UPDATE_IMAGE configurations, tooPatrick Georgi
This fixes UPDATE_IMAGE builds, assuming that the fmap configuration in the tree didn't change, at least as far as the CBFS regions are concerned. Another option would be to synthesize the fmap related files from the existing image, but that comes with other issues (eg. what about updating images old enough that there is no fmap?) and is more complex, so keep it simple, stupid for now. Change-Id: I036dab9f81f524f7d70bc0029b1ef835e6180a53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14601 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-05-05rdc/r8610: Move to src/socStefan Reinauer
Change-Id: I99e5d7f3b46c90ca863ddf6c186b5447d0c8e6f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14607 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-05dmp/vortex86ex: Merge northbridge and southbridge into socStefan Reinauer
Change-Id: I16c04452d2d6c3205aea29fe8aa8fad8fc485a46 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14600 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-05lib/reg_script: Fix bracesStefan Reinauer
In If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 the code was changed from one to two lines in the body of an if() statement, without adding braces. Change-Id: Ibbbdf240157adae95151fb2ce0135948caa60108 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14621 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-05soc/intel/quark: Add script time delay supportLee Leahy
Add time delay support to the scripts. TEST=Build and run on Galileo Gen2 Change-Id: I2c87977e2a2547e00769e59e1ee81fbbb5dff33f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14555 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-05soc/intel/quark: Add temperature sensor supportLee Leahy
Migrate the temperature sensor support from QuarkFspPkg into coreboot. TEST=Build and run on Galileo Gen2 Change-Id: I6dc68c735375c9d1777693264674521f67397556 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14565 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04soc/intel/quark: Add USB PHY initializationLee Leahy
Add register access support using register scripts. Initialize the USB PHY using register scripts. TEST=Build and run on Galileo Gen2 Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14496 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04drivers/xpowers: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Idae5ee5f1f48d904b704abe618165c0bec839979 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04buildgcc: Update Python to 3.5.1Stefan Reinauer
Change-Id: I57f935b94ab0db2e9ff9434fb496d470bb4ec987 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14463 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-05-04buildgcc: Update gdb and expatStefan Reinauer
Update gdb to 7.11 and expat to 2.1.1 riscv64-elf is still broken. Change-Id: Id7605f4274fcb15f9c3e366f5c492328f70f7956 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14461 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-05-04crossgcc: Update toolchainIru Cai
New tools: * mpfr 3.1.4 * binutils 2.26 * gcc 5.3.0 * llvm/clang 3.8.0 Patch changes: * binutils-2.25_fix-aarch64.patch: fixed in 2.26 * binutils-2.25_host-clang.patch: the positions of header file includes have been adjusted * binutils-2.25_no-bfd-doc.patch: update to 2.26 * binutils-2.25_riscv.patch: update from riscv-gnu-toolchain * gcc-5.2.0_elf_biarch.patch: update to 5.3.0 * gcc-5.2.0_gnat.patch: update to 5.3.0 * gcc-5.2.0_libgcc.patch: update to 5.3.0 * gcc-5.2.0_nds32.patch: update to 5.3.0 * gcc-5.2.0_riscv.patch: update from riscv-gnu-toolchain * cfe-3.7.1.src_frontend.patch: update to 3.8.0 In the latest code of riscv-gnu-toolchain project, the patch for {binutils,gcc}/config.sub has been removed, and the target is renamed as riscv32 and riscv64. The `riscv' to `riscv64' change in xcompile is in another commit. Test results: All GCC and LLVM/clang toolchain build successfully. x86,arm: qemu boots power8: firmware fails to boot aarch64,mips: not tested riscv: firmware fails to build with new binutils clang: firmware fails to boot Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I42ce89c29263d768d161c28199994f17d0389633 Reviewed-on: https://review.coreboot.org/14227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-04soc/apollolake: Set BootMode based on previous sleep stateRavi Sarawadi
- fill_power_state makes a copy of the current snapshot of power management registers in CAR variable "power_state" for use in ramstage - migrate_power_state adds CAR variable "power_state" to CBMEM (CBMEM_ID_POWER_STATE) - s3_resume state is updated in romstage_handoff block Change-Id: I842b85c5e562893b58cd3b3f6432695fbd4430bf Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/14550 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04soc/apollolake/romstage: Do not cast const to non-const pointersAlexandru Gagniuc
That was a workaround for the MRC cache API, which has since been reworked. The workaround is no longer needed. Change-Id: I1c1883f3ea37245615248459cd993ed774bf92de Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14574 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-04soc/intel/common/mrc_cache: Honor MRC data as a constant pointerAlexandru Gagniuc
The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-04nb/intel/sandybridge/raminit: support calling dram_freq multiple timesPatrick Rudolph
The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04nb/intel/sandybridge/raminit: add additional fallbacksPatrick Rudolph
Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14173 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04nb/intel/gm45: Fix native text mode initializationNick High
The LVDS port is configured to accept data from pipe A, but the panel fitter and VGA were attached to pipe B. Changes to VGACNTRL: - select pipe A instead of pipe B. - disable VGA centering to fix jitter. TEST=Build and run on Thinkpad X200 in both text and framebuffer modes. Change-Id: I2356f264580d8b021952c217de3477291d866f98 Signed-off-by: Nick High <nhigh@openmailbox.org> Reviewed-on: https://review.coreboot.org/14524 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-05-04lib/reg_script: Add display supportLee Leahy
Add the ability to enable the display of the script: * Added REG_SCRIPT_COMMAND_DISPLAY to enable and disable display output * Added context values to manage display support * display_state - Updated by the command to enable or disable display * display_features - May be updated by step routine to control what the step displays for register and value * display_prefix - Prefix to display before register data * Added REG_SCRIPT_DISPLAY_ON and REG_SCRIPT_DISPLAY_OFF macros to control the display from the register script * Added REG_SCRIPT_DISPLAY_REGISTER and REG_SCRIPT_DISPLAY_VALUE as two features of the common display. With these features enabled the following is output: * Write: <optional prefix> register <-- value * Read: <optional prefix> register --> value TEST=Build and run on Galileo Gen2 Change-Id: If0d4d61ed8ef48ec20082b327f358fd1987e3fb9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14553 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04crosfirmware: Make script more silentJoseph Pillow
Remove debug output and parted messages. Change-Id: I6416a88b5fdb4c92741439e9edb5f753f885cbe3 Signed-off-by: Joseph Pillow <joseph.a.pillow@gmail.com> Reviewed-on: https://review.coreboot.org/14460 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04soc/intel/fsp_baytrail: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I709ea938b720f26b351a1f950593efe077edb997 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14581 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-05-04soc/intel/baytrail: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c5d678d7adb4c489752cca80b20f785ec8749d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14580 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-04cpu/x86: combine multiprocessor and SMM initializationAaron Durbin
In order to reduce code duplication provide a common flow through callback functions that performs the multiprocessor and optionally SMM initialization. The existing MP flight records are utilized but a common flow is provided such that the chipset/cpu only needs to provide a mp_ops structure which has callbacks to gather info and provide hooks at certain points in the sequence. All current users of the MP code can be switched over to this flow since there haven't been any flight records that are overly complicated and long. After the conversion has taken place most of the surface area of the MP API can be hidden away within the compilation unit proper. Change-Id: I6f70969631012982126f0d0d76e5fac6880c24f0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14557 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin
Unconditionally provide the backup default SMM area API. There's no reason to guard the symbols behind anything since linker garbage collection is implemented. A board or chipset is free to use the code or not without needing to select an option. Change-Id: I14cf1318136a17f48ba5ae119507918190e25387 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14561 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04broadwell/me: Fix out-of-bounds array access errorEvan Lojewski
Fix an issue where a broadwell machine without the ME installed could result in an invalid status code being reported. For certain values, this would result in the intel_me_status function never returning. Fix has been tested on a samus board w and w/o the ME blob installed. Change-Id: I96667d3b89393f161e4d4efe0544efac98367e6c Signed-off-by: Evan Lojewski <meklort@gmail.com> Reviewed-on: https://review.coreboot.org/14409 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-04cpu/x86/smm_module_loader: always build with SMM module supportAaron Durbin
The SMM module loader code was guarded by CONFIG_SMM_TSEG, however that's not necessary. It's up to the chipset to take advantage of the SMM module loading. It'll get optimized out if the code isn't used anyway so just expose the declarations. Change-Id: I6ba1b91d0c84febd4f1a92737b3d7303ab61b343 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14560 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-04buildgcc: Always set HOSTCFLAGSNico Huber
Always set HOSTCFLAGS to the flags GMP was built with, defaulting to "-Os" if it isn't built yet. Previously, if GMP was already built or not even in the list of packages to be built, this was silently skipped and other packages were built with empty HOSTCFLAGS. Change-Id: I29b2ea75283410a6cea60dc1c92b87573aebfb34 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/13550 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-04payload: Fix broken Linux kernel as payloadWerner Zeh
Commit 785a31d67e8f34065a2483080e4fd7032c3a8aad (Makefile.inc: Move payload code to payloads/) breaks the usage of Linux kernel as payload. The reason for it is that cbfs-files-y is evaluated before payloads/external/Makefile.inc is sourced and as a consequence ADDITIONAL_PAYLOAD_CONFIG is empty when it is used for payload options. That leads to missing command line and initrd for the kernel which in turn leads to kernel panic when it boots. To avoid it, move the code which adds payload to cbfs completely to payloads/extranal/Makefile.inc. This way, ADDITIONAL_PAYLOAD_CONFIG is set right before the payload itself is added to cbfs-files-y. I have tested this patch with a Linux kernel as well as with SeaBIOS as payload on mc_tcu3 and it works. If someone sees impact to other payloads just let me know. Change-Id: I7aad352f8b3fc1fdba1875b12648b07eba14e282 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14579 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-04buildgcc: Use smaller xz archivesStefan Reinauer
The xz archives are slightly smaller than the bz2 archives for gmp and mpfr, so use them instead to speed up the download. Change-Id: I3729455cdbc46e5a0cff119ecca97b0e00c3d402 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14462 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-04buildgcc: Drop --target from python and expatStefan Reinauer
Both packages are not using the target architecture. Drop it, and remove them from package_uses_targetarch Change-Id: I58efde4cb7cc39e7e3c31527eb7682e318928100 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14464 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-03soc/intel/quark: Add IntelQNCConfig.h from EDK-IILee Leahy
Add the EDK-II Quark file IntelQNCConfig.h. This adds the definitions for the temperature sensor. TEST=Build and run on Galileo Gen2 Change-Id: I70896e6187b878ea572535432912f1d4db895a99 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14497 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-03mainboard/intel/galileo: Enable I2C and GPIOLee Leahy
Enable the I2C and GPIO controllers TEST=Build and run on Galileo Gen2 Change-Id: I97bbbb7c5e72edbed14702a4129d9cfa977e1911 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14558 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-03vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.hLee Leahy
Update the file to match the QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: I090578d32165d34863548aec0e4a38fe915683c6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14452 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-03chromeos: Ensure that the last file in FW_MAIN is not also the first onePaul Kocialkowski
In the case where one of the FW_MAIN regions is empty, the last file (empty) will also appear to be first and have a zero offset, making head complain. This is a very borderline use case, since the FW_MAIN_ regions should have been filled previously, but an extra check doesn't hurt. Change-Id: I15491c5b4a5e7d1f9fb369cc5fa4e3875e2dad3b Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-03nvramcui: Cast u8 * values to char * to eliminate warningsMartin Roth
error: pointer targets of 'strcmp' differ in signedness expected 'const char *' but argument is of type 'u8 * {aka unsigned char *}' Change-Id: Id5cbb6fc2efd7c57abc59b08416047e10461436f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14521 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-03intel/baytrail: use fmap information for code cachingPatrick Georgi
Instead of using CBFS_SIZE from Kconfig, use values generated from fmap. While at it, make sure that the cached region size is a power of two. fmap_config is also added to cpu_incs-y, but that doesn't hurt (except for some miniscule increase in compile time) because it's #if-guarded. The upside is that dependencies are tracked properly. Change-Id: I03a919e1381ca3d0e972780b2c7d76c590aaa994 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-03lib/cbfs: Use fmap derived information about the COREBOOT regionPatrick Georgi
It used to use CONFIG_CBFS_SIZE. The plan is that CBFS_SIZE only informs default*.fmd generation, while everything else derives its information from there. Also document the existing assumption that boot media should access the COREBOOT region (and not any other potentially existing fmap region containing a CBFS). Change-Id: I08254e4510f71edf99c2c8b56ac8f92008727c4a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14572 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03fmaptool: Export some fmap knowledge to the build environmentPatrick Georgi
By exporting base and offset of CBFS-formatted fmap regions, the code can use these when it's not prudent to do a runtime lookup. Change-Id: I20523b5cea68880af4cb1fcea4b37bb8ac2a23db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03build system: rename fmap.h to fmap_config.hPatrick Georgi
There's an in-tree fmap.h, and the file generated by fmaptool is likely used in tandem with it. To avoid problems, rename the generated file (which so far isn't used). Change-Id: I95dfde513a7f78677cf18ecd7ce8745e40af316b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03arch/x86: Drop CBFS_BASE_ADDRESSPatrick Georgi
It's unused. Change-Id: I50af2b50d2c5a7a24afe9099c5c01d17ce54a6c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFSPatrick Georgi
It's unused. Change-Id: I853702e40dcab9f193b2a3de7deeec80ab1d25f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14568 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-03build system: remove CBFSTOOL_PRE1_OPTSPatrick Georgi
It isn't used anymore. Change-Id: Ie554d1dd87ae3f55547466e484c0864e55c9d102 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14567 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-03.gitignore: add build and libpayload dirs for nvramcui payloadStefan Tauner
Change-Id: I8a29ca1b07df68b50ab54276c9d9b32a81308e02 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/14562 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-03xcompile: test if gcc is really availableStefan Tauner
Just because an 'as' with a certain prefix is available does not guarantee that a 'gcc' with the same prefix is available as well. Without a check detect_compiler_runtime() would try to execute an unavailable binary and print something like this: .../xcompile: line 218: arm-linux-gnueabi-gcc: command not found Change-Id: Icbadfeb2860152f7cf7696a9122521d0d881f3aa Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/14563 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-03board_status/towiki: Link to CGit instead of GitwebJonathan Neuschäfer
Gitweb isn't online anymore, so fix a few broken links. Change-Id: I7fdfcb60f83a718c9a5b6c7f7ef4df9206451d95 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14559 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-02soc/intel/quark: Remove UPD parametersLee Leahy
Remove the UPD parameters to match QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-02cpu/x86/mp_init: remove unused callback argumentsAaron Durbin
The BSP and AP callback declarations both had an optional argument that could be passed. In practice that functionality was never used so drop it. Change-Id: I47fa814a593b6c2ee164c88d255178d3fb71e8ce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14556 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-02drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE usedAaron Durbin
The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Remedy this failure by using the common car_stage_entry symbol for taking over control flow. Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02arch/x86/assembly_entry: allow early post CAR stages to use common codeAaron Durbin
The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. The normal path for romstage would be to reload the gdt, however in the previously described scenario has verstage performing that work. Therefore, provide that path under those conditions. The only difference from the C_ENVIRONMENT_BOOTBLOCK scenario is that the stack should not be reloaded since there's no way to know the top of the stack. Change-Id: Ic39ab52a856233d3042ac02a15ae4816ddfe07c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14548 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02arch/x86/asembly_entry: reorder conditional stage entry macrosAaron Durbin
The path that just clears CAR_GLOBAL variables and jumps to the stage entry point needs another condition for separate verstage just after bootblock. However, the current conditional is a negative conditional so swap the logic around to make it easier to extend. Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14547 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 06:14:21 +0000