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2016-05-09google/oak: Add derivative board ElmJulius Werner
This patch adds a new mainboard Google/Elm as a derivative of Google/Oak, using the same code sharing technique for derivative boards that was pioneered with Google/Veyron*. For now, there are no firmware-relevant fundamental differences between the two boards. In addition, introduce a board-specific Kconfig for the "board ID adjustment" to represent the fact that the Elm board ID space mirrors the Oak board ID space with an offset of 6, meaning Elm rev0 is equivalent to Oak rev6, and future board changes will be made on both boards to maintain this stride (at least virtually... not all of those revisions will necessarily get built). This should make it much easier to keep the code that handles revision differences somewhat clean. (That's the theory, anyway... whether it will work out remains to be seen.) BRANCH=None BUG=None TEST=Booted Elm image with hardcoded board ID 0 on Oak rev6. Change-Id: If540aea862b746cf4986a74482ae1764c104fb73 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53cd85c94945ab0bf14cb88a98e66723fc4483de Original-Change-Id: Ib05fc81dc4f4308d99e34fce74c6db8b323785da Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332276 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: configure displayJitao Shi
BRANCH=none BUG=chrome-os-partner:43706 TEST=saw bootloader screen on rev4 and rev5 Change-Id: I844fed6f63467ad04d17115934a1e4724cc0b671 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2e9d57a42402631923c96e70bc2eff5c135de2fc Original-Change-Id: I748b0eac9a0aab1d38d5d44a1a50dc33d5375379 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331813 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/14690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09mediatek/mt8173: Add display driverJitao Shi
BRANCH=none BUG=none TEST=saw bootloader screen on rev4 and rev5 with CL:331813 Change-Id: Ibb01cf251276d2c059739f10e166fefd0de35460 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d52a4c486b75b99dc25657ccb6ed90f671c26d6 Original-Change-Id: I4efe439d52b5a5516145960bcffb340152bfba53 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331812 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/14689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09ec/google/chromeec/acpi: Add GOOG0004 to load cros_ec_lpc dynamically.Gwendal Grignou
Add a GOOG0004 object that will be used to load cros_ec_lpc. BUG=chromium:516122 BRANCH=none TEST=Compile. Work in cyan branch. Change-Id: Id8d9487ea6f376728eaa57728baceda7e5f6b2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6380104986d2740a14fc74161fec9f2994d2affc Original-Change-Id: I682d68e0858327ec7c0fbd0924dd9f99527d4df0 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342363 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload/arm64: Mark existing framebuffer as DMAablePatrick Georgi
If a framebuffer is already configured by coreboot, libpayload's MMU tables didn't mark its memory DMAable (unlike when libpayload set up its own framebuffer memory). BRANCH=none BUG=chrome-os-partner:52826 TEST=depthcharge's recovery screen is not corrupted anymore on kevin Change-Id: I228a861b3fdcf1298a3cfa0a054214c78ed55e70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889e8358a0f2f504abd9910549aa68f3992bb4e8 Original-Change-Id: I7ba79151ccc1eb605f82e1869a74b539a6be5e99 Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341092 Reviewed-on: https://review.coreboot.org/14685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09spi: Add support for Winbond W25Q256Varadarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ifde289ec004f5d54d5df32011c87e49470e2bb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 613b5ae45f7b8325863d8be492a451e6d076e293 Original-Change-Id: I93386e058a60b5c9b61d89607cf8c6e0de6a21ca Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/334522 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload: xhci: Set MPS based on speedVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Compiles and boots and detect USB storage BRANCH=none Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3 Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333311 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14659 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09soc/intel/skylake: Enable another VR mailbox command for certain boardsSubrata Banik
Command List: Send command for PS4 exit fails BUG=chrome-os-partner:52355 BRANCH=glados TEST=Build and boot lars and verify no hang during active idle CQ-DEPEND=CL:*257305 Change-Id: I9ffae71b1a38433ffc48ee7be7e2a13e69ad5b87 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96f00e2d153f92339c378ce256eb7ce6824e3368 Original-Change-Id: I320ae154f3f7145811b57258ddb61b3beb584273 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341330 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14688 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09soc/intel/skylake: Output more ME status informationDuncan Laurie
Output a few more status bits from HFS/HFS2 and add some interesting bits from HFS3. BUG=chrome-os-partner:52662 BRANCH=glados TEST=boot on chell and verify ME status output Change-Id: I989b680f203678dbe28559e858faf8b4e0837481 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ea34ab019da3fff965102bcef5158ddcc154728 Original-Change-Id: Iff977c8d85b4d4dfa00b5b19bc29d11813a99b9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340390 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/14687 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-09libpayload: Add nyan configPaul Kocialkowski
This adds a nyan libpayload config, that should fit all nyan devices. Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14473 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra124: Align the framebuffer's bytes-per-line to 32Paul Kocialkowski
It turns out that tegra124 needs the framebuffer's bytes-per-line to be aligned to 32 for proper display. This behaviour was default before moving to edid_set_framebuffer_bits_per_pixel. This fixes display on nyan_big. Change-Id: Ie81b395fca23f3648ea7cd1df51152faea864c9a Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14564 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra132, tegra210: Align the framebuffer's bytes-per-line to 64Paul Kocialkowski
It turns out that tegra132 and tegra 210 need the framebuffer's bytes-per-line to be aligned to 64 for proper display. This behaviour was default before moving to edid_set_framebuffer_bits_per_pixel. Change-Id: I46dadcf36e1c50e9649121ee6fa9cdf6134a531e Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14734 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra132, tegra210: Fix "becasue" typo in commentsPaul Kocialkowski
This renames "becasue" occurrences to "because". Change-Id: I7862ce6a865cb1525ca1cef69c2eb1e90cc76a9d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14735 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-093rdparty/arm-trusted-firmware: update to current masterPatrick Georgi
It includes support for rk3399. Change-Id: I326ef3dc3021313ee852395c302c076b3e3c8c5e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14732 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09arch/armv7: Fix end index calculation in mmu_config_range_kbVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ib0fccfe2d103710c006cb3950c65b11b8d596912 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9be5f58bb89ec43d4eb264c94c3f745dcade35dd Original-Change-Id: If50efb55d4974dfcab07d3ae6488c2413b505a1f Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333301 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14657 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins)
2016-05-09siemens/mc_tcu3: Fix spelling of *set up*Paul Menzel
The verb *set up* is written with a space [1]. So correct that in the function descriptions. [1] http://www.merriam-webster.com/dictionary/set%20up Change-Id: Icf5aa7eca2c379fdf7ff1935d71efc347f5ce6fa Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14701 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09siemens/mc_tcu3: Add blank lines for better legibilityPaul Menzel
Change-Id: I6d1200dd59e53ca892594c1fce784639a9817550 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09siemens/mc_tcu3: Remove unneeded variable assignmentPaul Menzel
Assigning the value `1` to `status` in the default branch of the switch statement is not needed, as the stored value is overwritten before it can be used. Change-Id: I532b0e217ff4ed315cd30b08d339c755c6df7539 Found-by: Coverity, CID 1355008: Code maintainability issues (UNUSED_VALUE)) Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09lib/prog_loaders: Allow platforms to skip stage cacheFurquan Shaikh
Before multi-CBFS support was added, x86 platforms cached their ramstage in TSEG so that it could be re-used on the resume path. However, more resources/assets are being put in cbfs that are utilized during ramstage. Just caching ramstage does not mean that correct cbfs region is used for all the data. Thus, provide an option to allow platforms to skip caching any component for resume. Change-Id: I0e957a6b859cc7d700aaff67209a17c6558be5de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-09xip: Do not pass --xip for early stages if CAR supports code executionFurquan Shaikh
On modern x86 platforms like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is default false for all x86 platforms. Apollolake selects this option since it supports code execution with CAR. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-08util/sconfig: Fix warningsStefan Reinauer
and re-generate _shipped files Change-Id: I7a18824d64d3f6212e8566695376bf97e2196ee2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14733 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-05-08intel/pineview: Don't try to store 34 bits in 32Stefan Reinauer
Mask out the bit that doesn't fit in 32bits, so gcc 6.1 is happy Change-Id: I13e2b41742206b8d86b90314b80cc324c00ae637 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14639 Reviewed-by: Damien Zammit <damien@zamaudio.com> Tested-by: build bot (Jenkins)
2016-05-08parade/ps8640: Initialize edid_sizePatrick Georgi
decode_edid either gets EDID_LENGTH bytes or (in the extended case), 2*EDID_LENGTH. See that this is reflected in its size argument. Change-Id: If6c76358db4e9ee01c2bd2dbdd5948c61b7aa5bc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14698 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-07board_status: Allow for parsing longoptsDavid Hendricks
This converts the argument parsing to allow us to add longopts using GNU getopt(1). Shortopts should be reserved for general parameters. Longopts can be used to tweak specific behaviors. For example, we might wish to add options to set SSH port, timeout, and authentication parameters with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc. Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14523 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-05-07google/foster: Configure audio codec padsStefan Reinauer
Otherwise, newer GCCs will insist that they get deleted. Change-Id: Ida45b7d193366f5e611a32632ba610193451b082 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14619 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06amd/gx2 + amd/lx: Fix shift overflow issueStefan Reinauer
gcc 6.1 complains that SMM_OFFSET << 8 is larger than the register it is assigned to (rightly so): src/northbridge/amd/gx2/northbridgeinit.c:196:23: error: result of '1077936128 << 8' requires 40 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] msr.lo = (SMM_OFFSET << 8) & 0xfff00000; ^~ Change-Id: Ib0d669268202d222574abee335a6a65c8a255cc7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14617 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06rtc: Do checksum check for all bytesStefan Reinauer
Due to missing braces (that went undetected because of the indentation), I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 CMOS: add set_option() only takes the last changed byte into regard when determining whether the checksum needs to be updated. This bug went undetected for 5 years. Change-Id: I47cedc801a60959386dfdcda3a13b8e3162a7ecb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06drivers/intel/fsp2_0: Update to FSP draft 9Andrey Petrov
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This change keeps FSP driver code in sync with header changes. Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06ec/google/chromeec/ec_lpc: Declare used IO ports as a resourceAlexandru Gagniuc
Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14585 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-06soc/apollolake/lpc: Allow configuring SERIRQ via devicetreeAlexandru Gagniuc
Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ continuous mode. Why they do that is beyond me, but the way we implement it on apollolake is via devicetree. Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Declare ChromeEC in devicetree.cbAlexandru Gagniuc
This allows the chomeec driver to declare its resources so that IO windows to LPC are opened up during resource allocation. Change-Id: Ife98ecb4cbf5393493e6c71742de8d37953df548 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Check with EC if we should enter recovery modeAlexandru Gagniuc
Change-Id: Id35a74e3968315659b323e0ba348ad38ca11981b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06ec/google/chromeec/ec_commands.h: Include stdint.hAlexandru Gagniuc
This file use stdint types, but does not include the appropriate header. This creates a parasitic dependency on including stdint.h before ec_commands.h. Fix that by including the necesarry header. Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Configure the bridge to ChromeEC in the bootblockAlexandru Gagniuc
Communication with ChromeEC, which is on the LPC bus, is needed early on for vboot purposes. I'm not sure if Google wants to have the interface available in bootblock or romstage, so we're confguring it in the bootblock. The bridge is automatically reconfigured during ramstage in a way in which we don't get duplicate windows opened upt to LPC. Change-Id: I77887e881d23f655495dec2687394409a5bb8cf5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14588 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06soc/apollolake/lpc_lib: Add utility to configure LPC padsAlexandru Gagniuc
Change-Id: Iaf325863681ad9b8b5d7662a9d267488b8fdf008 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06soc/apollolake/lpc: Open I/O to LPC based on resource allocationAlexandru Gagniuc
Besides a number of fixed memory windows, Apollolake supports opening a configureable 64 KiB MMIO window, as well as four PMIO windows to the LPC bus. Open up these windows dynamically, based on how resources were allocated to the child LPC devices. Change-Id: I170e861693cb6fd1be38889adc951f197a13460f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06Revert "soc/intel/apollolake: Enable LPC bus interface"Alexandru Gagniuc
This reverts commit e976bd44692d2adb320a1256f1b6bfaa6469108a. The LPC resource allocation will be completely reworked in subsequent patches. The most straightforward approach is to start by reverting the existing code. Change-Id: I2475542b79817020d4c956f22ed5856f05046b16 Reviewed-on: https://review.coreboot.org/14583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06intel/amenia: Do not manually open up IO windowsAlexandru Gagniuc
Do not use devicetree.cb to manually control hardware registers. This interface will be removed in a subsequent commit and replaced with runtime allocation that also does sanity checking. Change-Id: I55561085ea467f19f52110b1a59f45fe290c7f09 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06soc/intel/apollolake: fix incorrect bdsm -> tolud memory resourcesAaron Durbin
The wrong base address was being used for the region of memory between BDSM and TOLUD. This resulted in a very large reserved region starting at TOLUD instead of BDSM. Change-Id: I41d06267ffa93ea47aa059f4ddb7b9c349e51583 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14628 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06soc/intel: indicate to build system that XIP_ROM_SIZE isn't usedAaron Durbin
The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets. Therefore, indicate as such so that romstage can be placed in cbfs less rigidly. Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14626 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZEAaron Durbin
Previously, the XIP_ROM_SIZE Kconfig variable is used globally on x86 platforms with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened by not passing '-P $(XIP_ROM_SIZE)' to cbfstool when adding romstage. Change-Id: Id8692df5ecec116a72b8e5886d86648ca959c78b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14625 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06util/cbfstool: fix x86 execute-in-place semantics for all fmd regionsAaron Durbin
A previous patch [1] to make top-aligned addresses work within per fmap regions caused a significant regression in the semantics of adding programs that need to be execute-in-place (XIP) on x86 systems. Correct the regression by providing new function, convert_to_from_absolute_top_aligned(), which top aligns against the entire boot media. [1] 9731119b cbfstool: make top-aligned address work per-region Change-Id: I3b685abadcfc76dab8846eec21e9114a23577578 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14608 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
There used to be a need for an empty smm_init() function because initialize_cpus() called it even though nothing called initialize_cpus(). However, garbage collection at link time is implemented so there's no reason to provide an empty function to satisfy a symbol that is completely culled during link. Remove it. Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14605 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06cpu/x86/mp_init: reduce exposure of internal implementationAaron Durbin
With all users converted to using the mp_ops callbacks there's no need to expose that surface area. Therefore, keep it all within the mp_init compilation unit. Change-Id: Ia1cc5326c1fa5ffde86b90d805b8379f4e4f46cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14598 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/skylake: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c4674ed258922b6616d75f070df976ef9fad209 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14597 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06cpu/intel/haswell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I80b5b94b62bdd001581eb56513a0d532fffb64e8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14596 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06soc/intel/broadwell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I74c81c5d18dff7a84bfedbe07f01e536c0f641fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14595 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06soc/intel/apollolake: convert to using common MP initAaron Durbin
In order to reduce duplication of code use the common MP initialization flow. Change-Id: I8cfb5ba6f6a31fecde2ce3bf997f87c4486ab3ab Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14594 Tested-by: build bot (Jenkins) Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/braswell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I65beefec53a29b2861433bc42679f3fa571d5b6a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14593 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/fsp_broadwell_de: convert to using common MP initAaron Durbin
In order to reduce duplication of code use the common MP initialization flow. Change-Id: I2a7c628cfae7cf6af6e89fa8fc274f59127ff7c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14592 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
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