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2014-04-02superio/fintek/f71863fg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I863c16634873224c17e43100271e9b91419724d0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5435 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71805f: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5434 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-01x86: use car_(get|set)_var accessors for apic timerAaron Durbin
The timer_fsb variable was not correctly being accessed in the presence of cache-as-ram. The cache-as-ram backing store could be torn down but then udelay() could be called causing hangs from accessing variables that have unknown values. Instead change the timer_fsb variable to g_timer_fsb and obtain the value through a local access method that does the correct things to obtain the correct value. Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5411 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-04-01Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATEKyösti Mälkki
Use of CAR_GLOBAL is not safe after CAR is torn down, unless the board properly implements EARLY_CBMEM_INIT. Flag vulnerable boards that only do cbmem_recovery() in romstage on S3 resume and implementation with Intel FSP that invalidates cache before we have a chance to copy the contents. Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-01git-ignore site-localPatrick Georgi
It's _local_ Change-Id: I5624e240ffe486763b25b14b218e69362c488f50 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5432 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-31superio/fintek/f81865f: Avoid .c includesEdward O'Callaghan
We should not be #include .c files, instead link early_serial into romstage and provide a prototype. Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5416 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-29cubieboard: Enable the SD controller and mux SD pinsAlexandru Gagniuc
This step needs to be done before calling any MMC functionality. Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4745 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-28mainboard/hp: Add initial support for Pavilion m6-1035dxAlexandru Gagniuc
This was a pathetically easy port, where all the components are already supported. This is basically a verbatim copy of amd/parmer. The EC is an ENE KB932, which is a part that does surprisingly little for an EC. This also means we need almost no code to get it working. I've "select"ed the EC in Kconfig, which is the only difference from parmer, although the keyboard worked fine without it. I haven't coupled in the ACPI code from the EC yet, so battery level is not readable from the OS. Hotkeys work except for brightness control, and the CapsLock LED blinks at regular intervals instead of following the CapsLock key. Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5409 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-28mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`Paul Menzel
It's not needed and causes build failures without CONFIG_CHROMEOS. Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5398 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-28cbfstool: provide structure to linux payload builderAaron Durbin
This change started with tracking down a bug where the trampoline size was not being taken into account for sizing the output buffer leading to a heap corruption. I was having a hard time keeping track of what num_segments actually tracked as well as what parts were being placed in the output buffer. Here's my attempt at hopefully providing more clarity. This change doesn't crash when adding a bzImage: $ dd if=/dev/zero of=bb.bin bs=64 count=1 $ ./cbfstool tmp.rom create -s 4M -B bb.bin -m x86 -a 64 $ ./cbfstool tmp.rom add-payload -f ~/Downloads/bzImage -C "1" -n "fallback"/payload Change-Id: Ib1de1ddfec3c7102facffc5815c52b340fcdc628 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5408 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-27util/superiotool: Add initial support for Fintek F71869ED.Wilbert Duijvenvoorde
Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf Practically the same as F71869AD, just another ID (0x1408). Tested on actual hardware, Jetway NC9C-550-LF. Update: Fixed F71869ED based on the proper datasheet: http://www.alldatasheet.com/datasheet-pdf/pdf/459075/FINTEK/F71869ED.html Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com> Reviewed-on: http://review.coreboot.org/5380 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-26mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in KconfigEdward O'Callaghan
Switch on ACPI suspend/resume support which now works after many cycles. Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5406 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-03-24util/superiotool: Register fix for Fintek F71869ADWilbert Duijvenvoorde
Fixed F71869AD based on the proper datasheet: http://www.alldatasheet.com/datasheet-pdf/pdf/459074/FINTEK/F71869AD.html Change-Id: If22341551c6a1a9bbae088801a6194f7b5b6bf4d Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com> Reviewed-on: http://review.coreboot.org/5405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-24mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cbEdward O'Callaghan
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5401 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-20rmodules: use rmodtool to create rmodulesAaron Durbin
Start using the rmodtool for generating rmodules. rmodule_link() has been changed to create 2 rules: one for the passed in <name>, the other for creating <name>.rmod which is an ELF file in the format of an rmodule. Since the header is not compiled and linked together with an rmodule there needs to be a way of marking which symbol is the entry point. __rmodule_entry is the symbol used for knowing the entry point. There was a little churn in SMM modules to ensure an rmodule entry point symbol takes a single argument. Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5379 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-03-20util: add rmodtool for parsing ELF files to rmodulesAaron Durbin
The current implementation of creating rmodules relies on invoking the linker in a certain manner with the relocations overlaid on the BSS section. It's not really surprising that the linker doesn't always behave the way one wants depending on the linker used and the architecture. Instead, introduce rmodtool which takes an ELF file as an input, parses it, and creates a new ELF file in the format the rmodule loader expects. Change-Id: I31ac2d327d450ef841c3a7d9740b787278382bef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5378 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-18cbfstool: add ELF writing supportAaron Durbin
In order to generate rmodules in the format of ELF files there needs to be support for writing out ELF files. The ELF writer is fairly simple. It accpets sections that can be associated with an optional buffer (file data). For each section flagged with SHF_ALLOC a PT_LOAD segment is generated. There isn't smart merging of the sections into a single PT_LOAD segment. Change-Id: I4d1a11f2e65be2369fb3f8bff350cbb28e14c89d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5377 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-17mainboard/lenovo/x230 Fix usage of GNU field designator extensionEdward O'Callaghan
In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5392 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-17romcc.c: Fixes warning about unused function from unused macros.Edward O'Callaghan
GCC suppresses warnings about unused static functions if they are inline, however Clang only does this for header files. None of these MASK_ declarations are used, so just remove them. Change-Id: Ia230beba3f6367237838d9b3d90536459e1d52cb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5273 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-16Make POST device configurable.Idwer Vollering
Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4561 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-14cbfstool: add symbol table parsing to the ELF parserAaron Durbin
Optionally parse the symbol table contained within an ELF file. It currently assumes there is only one symbol table present, and it errors out if more than one is found. Change-Id: I4ac4ad03184a319562576d8ab24fa620e701672a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5376 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14cbfstool: add string table parsing to ELF parserAaron Durbin
Optionally parse the string tables within an ELF file. Change-Id: I89f9da50b4fcf1fed7ac44f00c60b495c35555ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5375 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14cbfstool: add relocation parsing to ELF parserAaron Durbin
Optionally parse the relocation entries found within an ELF file. Change-Id: I343647f104901eb8a6a997ddf44aa5d36c31b44b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5374 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-14cbfstool: introduce struct parsed_elf and parse_elf()Aaron Durbin
In order to make the ELF parsing more flexible introduce a parse_elf() function which takes a struct parsed_elf parameter. In addition take a flags parameter which instructs the ELF parser as to what data within the ELF file should be parsed. Change-Id: I3e30e84bf8043c3df96a6ab56cd077eef2632173 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5373 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: remove incorrect section size checkAaron Durbin
I was overzealous in checking the section size with respect to the file size. That check makes no sense as the section only deals with link sizes -- not on-disk sizes. Remove the check as it doesn't make any sense. Change-Id: I348e7847ae3a50badc22693439614f813462445a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.Edward O'Callaghan
The target board has a different base addr. for its hardware monitor (fans, temp, etc) from the Fintek Super I/O datasheet. Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5383 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.Edward O'Callaghan
Fan controls in 0x400-0x4ff are not programmed here. Thus fan control from amd/persimmon in the devicetree.cb does not apply to this board. Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5381 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13cbfstool: elfparsing: check segment and section regionsAaron Durbin
While parsing the section and program headers ensure the locations of their contents are within the elf file proper. Change-Id: I856f7de45f82ac15977abc06e51bedb51c58dde1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5372 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: elfheaders: use proper parameters to calloc()Aaron Durbin
Though the result doesn't matter much, the callers of calloc() should order the parameters correctly. i.e. the first paramter is the number of elements in an array and the second is the size of each element. Change-Id: Ic7c2910d623d96f380feb4e5f6fa432376f49e9b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5371 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: add eflparsing.hAaron Durbin
elfparsing.h serves as the header to working with the elf parser. Additionally, only include what is needed by the other files. Many had no reason to be including elf.h aside from fixing compilation problems when including cbfs.h. Change-Id: I9eb5f09f3122aa18beeca52d2e4dc2102d70fb9d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5370 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: move iself() to eflheaders.cAaron Durbin
The only user of iself() was in elfheaders.c. Move it there, and make it local to the compilation unit. Change-Id: I0d919ce372f6e2fce75885fb4fcba20d985979b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-13cbfstool: elfheaders: use common checks and buffer helpersAaron Durbin
The elfheaders code was manipulating struct buffers. Use the introduced buffer helper functions. Additionally fix up offset and size checks for the program headers and section headers by using common code paths. Change-Id: I279c77f77aaa1860a0be43fb111df890dd1d84d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5368 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-03-12Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"Alexandru Gagniuc
This reverts commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce. This commit changed the board status script to describe all boards in terms of x86 terminology, such as CPU->southbridge->northbridge. This terminology does not apply to a number of SoCs, in which the buses are not connected via successive bridges, and as such it is misleading and misguided to describe ideas of southbridge and northbridge for these devices. Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5177 Tested-by: build bot (Jenkins)
2014-03-12drivers/spi: Add support for adesto SPI flash partsChris Douglass
Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5225 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11chromeos: provide option to dynamically allocate ram oops bufferAaron Durbin
Fixing the location of the ram oops buffer can lead to certain kernel and boot loaders being confused when there is a ram reservation low in the address space. Alternatively provide a mechanism to allocate the ram oops buffer in cbmem. As cbmem is usually high in the address space it avoids low reservation confusion. The patch uncondtionally provides a GOOG9999 ACPI device with a single memory resource describing the memory region used for the ramoops region. BUG=None BRANCH=baytrail,haswell TEST=Built and booted with and w/o dynamic ram oops. With the corresponding kernel change things behave correctly. Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11baytrail: Reserve memory between ASEG and 1MB and for ramoopsDuncan Laurie
Low system tables are in this region, and it is probably safer to keep ASEG reserved. Also keep the region used by ramoops from being used by the OS and from being cleared by developer mode boots. Lots more work needed to make the ACPI tables fully functional. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4932 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-11rambi: Enable USB boot with EHCI controllerDuncan Laurie
This adds the EHCI driver back to libpayload and configures the devicetree to route ports to EHCI. This is hopefully just temporary until the issues with XHCI can be worked out. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175513 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: Add EHCI initializationDuncan Laurie
This adds required steps to initialize the EHCI controller on the baytrail platform. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175512 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4930 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: Add XHCI initializationDuncan Laurie
This adds required steps to initialize the XHCI controller on the baytrail platform. Actually using XHCI is causing lots of bad behavior including apparent memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot on rambi Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175511 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4929 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: add audio clock workaround for LPEAaron Durbin
Apparently the LPE device needs a 25MHz clock. Provide the work around to enable this clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Confirmed setting being applied. Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175493 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4928 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: add ccu iosf access functionsAaron Durbin
The clock control unit needs to be accessed to configure some of the devices properly. Therefore. provide a way to access the CCU. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built. Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175492 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4927 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: HDA function disable workaroundAaron Durbin
Parts of the audio path are common between the HDA and LPE. However, those parts are power-controlled by the D-state of the HDA device. Therefore, one cannot put the HDA into D3Hot because those audio paths will be shutdown. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Disabling HDA still causes a shutdown when performing warm reset, however I was able to verify the magic sequence was being performed. Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175491 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4926 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: allow function disable on TXEAaron Durbin
Previously it was not known how to put the TXE pci device into D3Hot. It's been disseminated that this is not a requirement for disabling the TXE pci device in the function disable register. Therefore, allow this by returning 0 from place_device_in_d3hot(). BUG=chrome-os-partner:22871 BRANCH=None TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being set accordingly. Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175490 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4925 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11baytrail: Switch graphics init to use reg_scriptDuncan Laurie
This is an example consumer of the register script handler. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi and see recovery screen Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175214 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4924 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11cbfstool: add struct buffer helper routinesAaron Durbin
There are some open-coded manipulation of the struct buffer innards in the elf parsing code. Add helper functions to avoid reaching into the struct itself. Change-Id: I0d5300afa1a3549f87f588f976184e880d071682 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5367 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11cbfstool: add bputs() to store a byte stream to a bufferAaron Durbin
There was already a bgets() function which operates on a buffer to copy a byte stream. Provide bputs() to store a byte stream to a buffer, thus making the API symmetrical. Change-Id: I6166f6b68eacb822da38c9da61a3e44f4c67136d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11cbfstool: add get8/put8 variants to xdr structuresAaron Durbin
In order to provide consistent usage provide the get8() and put8() callbacks to xdr operations. That way no futzing needs to be done to handle 8-bit reads and writes. Change-Id: I1233d25df67134dc5c3bbd1a84206be77f0da417 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5365 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11cbfstool: move verbose to common.cAaron Durbin
In order for multiple tools to use the common code found in common.c place the verbose variable within common.c's compilation unit. Change-Id: I71660a5fd4d186ddee81b0da8b57ce2abddf178a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5364 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-11rmodule: allow rmodule header structure to be used by userlandAaron Durbin
In order for userland to create rmodules the common code should be shareable. Therefore, convert the short u<width> name types to the posix uint<width>_t types. Additionally, move the definition of the header structure to a new rmodule-defs.h header file so that userland can include that without pulling in the coreboot state. Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5363 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-10AMD Olive Hill: add IMC fan controlWANG Siyuan
There are 3 steps to enable the IMC fan control: 1. Enable fan control related registers on Hudson using oem_fan_control(). 2. Set EcStruct. 3. Enable thermal zone using enable_imc_thermal_zone(). I have tested on Olive Hill. Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4301 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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