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2017-12-20device/dram/ddr2.c: Store the checksum in the decoded SPD structArthur Heymans
Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-20drvs/lenovo/hybrid_graphics/romstage: Fix dGPU activationPatrick Rudolph
While the older boards use a GPIO that has no state, the newer boards' PMH7 does have a state, that even remains after reboot. Don't assume default values in PMH7 and instead always program it. Fixes dGPU doesn't show up when switching from integrated to discrete GPU. The workaround of removing all power is no longer necessary. Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20mb/google/poppy/variants/nautilus: Change USB2 phy settingsh.kim
In order to pass USB2 eye diagram, some USB2 port PHY registers needs to be changed. Port1 (Type-A): USB2_PORT_SHORT Port2 (BT): USB2_PORT_SHORT Port6 (H1): USB2_PORT_SHORT Port7 (Camera): USB2_PORT_SHORT BUG=none BRANCH=master TEST=emerge-nautilus coreboot and do eye-diagram test Signed-off-by: sh.kim <sh_.kim@samsung.com> Change-Id: I174e5bf96a53bb210481fb88298d5341f6c11dec Reviewed-on: https://review.coreboot.org/22686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20mb/lenovo/t430/acpi_tables: Don't set flvlPatrick Rudolph
The current fan level should be zero at boot and only be modified by ACPI or SMI code. Change-Id: I72b59f05746b28cfb24c4f018aebc2befa9caba6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-20intel/bd82x6x: Use generated ACPI PIRQTobias Diedrich
Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 (sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X. This generates the main ACPI _PRT table automatically based on the chipset registers. Tested on Intel NUC DCP847SKE with Linux 4.13.14: $ cat /proc/interrupts CPU0 CPU1 0: 23 0 IO-APIC 2-edge timer 8: 1 0 IO-APIC 8-edge rtc0 9: 0 0 IO-APIC 9-fasteoi acpi 19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1 23: 0 0 IO-APIC 23-fasteoi i801_smbus [...MSI and other interrupts skipped...] Log messages: ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6 ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4 ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4 ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8 ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1 Generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20sb/intel/common: Automatically generate ACPI PIRQTobias Diedrich
Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34 (sb/intel/common: Add function to automatically generate ACPI PIRQ). This adds functionality to generate PIRQ ACPI tables automatically based on the chipset registers. Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific intel_common_map_pirq() function, an shared implementation of which is provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint chipsets. Example generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20mainboard/intel/cannonlake_rvp: Disable SATA controllerVaibhav Shankar
SATA was enabled only for internal testing. Since we do not use SATA on chrome platforms, it can be disabled. Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20google/gru: Adjust to incorrect strapping resistors on KevinJulius Werner
It seems that RAM code 0 has been strapped with an incorrect resistor on Kevin. The resulting voltage divide still puts it well within the ADC value bucket reserved for that slot, but a little closer to the edge than necessary. While this doesn't seem to cause any immediate problems on its own, it still doesn't hurt to fix it (if only for the documentation value). On other boards (at least on my Scarlet) the strapping seems to be correct. Change-Id: Ic5199834fbeaf734e725ff45b04f45eefe149855 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22891 Reviewed-by: David Schneider <dnschneid@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20google/gru: Prettify strapping ID ADC tableJulius Werner
This patch shifts some comments around to make it easier to replace values in the ADC strapping bucket table with compile-time conditionals. Change-Id: Ic51917d3961a51d4e725ff824fb59aeefe149855 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20util/inteltool: Add GPU device IDsPatrick Rudolph
Add PCI device IDs for several Intel GPUs. Change-Id: I7d6ba16b2b115187fd57a31716f23a610b520d3e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-12-20soc/intel/denverton_ns: Add Denverton-AD system agent idLew, Chee Soon
This is to add support for Denverton-AD soc. Change-Id: I539abedd65bcbdb97b64f58d0b2273ff8eb67420 Signed-off-by: Lew, Chee Soon <chee.soon.lew@intel.com> Reviewed-on: https://review.coreboot.org/22605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20payloads/SeaBIOS: Add different MMIO uart configurationsPhilipp Deppenwiese
The MMIO address can change for different platforms like Apollolake. Change-Id: I6ec72d3a14f00212323a04e20d5a477dbc26b770 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20soc/intel/cannonlake: Tell FSPM UART port numberLijian Zhao
Cannonlake FSP will send debug message on selected UART port, use same coreboot UART debug port to FSP. TEST=Boot up with board have UART port 0 and can see the print of FSP Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20include/cpu/x86: Add clflush inline functionMarshall Dawson
Change-Id: I74c5cc22f02302314ba010bc599051c1495a13cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Add BootDone commandMarshall Dawson
After the PSP receives the MboxBiosCmdBootDone, it will no longer honor any command where the command-response buffer exists outside of SMM memory. Add the command and automatically execute it before booting the payload. BUG=b:69971683 TEST=Boot Kahlee and observe console log Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Convert structure init to C99Marshall Dawson
Use C99 designated initializers for the psp_notify_dram() buffer structure. Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Assume PSP command register already set upMarshall Dawson
Remove the frequent setting/restoring of the PSP's bus-mastering and memory decoding settings. It is up to the caller to ensure it is already set properly. Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/stoneyridge: Force PSP command reg settings in bootblockMarshall Dawson
A subsequent patch to the PSP library will rely on the device already having its PCI command register set to allow memory decoding and mastering enabled. Program the command register ahead of loading the SMU FW1 blob in bootblock. When the device has not been set up (e.g. when SMU FW is not selectable), AGESA sets up the device. As a result, a similar change is not required before sending the DRAM ready command. Change-Id: Id586106751286c4767b5c16ed7e1604523635492 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-20util/cbfstool: Check for NULL before dereferenceMartin Roth
Fixed coverity issue: 1302455 - Dereference null return value Change-Id: I59b908adc4d35f08fda8e4ad3f806714f2caeb65 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-20cpu/x86: set permanent SMM handler stack to 1KiBAaron Durbin
Not all SMM save state sizes equate to having enough stack in the permanent SMM handler. Therefore, ensure 1KiB of stack is available for each cpu's stack. Intel's save state size is 1KiB, but AMD's save state size is only 512. Therefore, decouple save state size from the per cpu stack size. BUG=b:70027919 Change-Id: I54b9e6f3cc0ad6ca3d7b60b2b422b5dc5a78a552 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-20intel/gma: fix RPNFREQ_VAL bitmaskFelix Held
gma.c of Nehalem was copied from Sandy/Ivy Bridge, so fix it there too. Tested on lenovo/x230. Since both the bit that was masked wrongly and the one that wasn't masked, but sould have been, are 0, the behaviour on lenovo/x230 doesn't change. Change-Id: I5f51c4929df83f948fcb7dc06e07ac3cc4ccf4f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/22596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-20mb/google/poppy/variants/nami: Add SPD files for namiFurquan Shaikh
This change adds SPD files for memory IDs 1-4 on nami. BUG=b:70182907 Change-Id: Ic43f944c0cde18244fe4c4d21314b831d048a3a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20mb/google/poppy: Enable speaker and codec for namiGaggery Tsai
Nami uses MAX98357A speaker amplifier and DA7219 codec. This patch adds max98357a and da7219 under I2C #3 in devicetree and adds SPK DMIC nhlt support for 4CH DMIC. BUG=b:70646770 TEST=emerge-nami coreboot Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-19mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTSIru Cai
ACPI bit is not set after an S3 resume, so set it in _WAK. Setting SLPT bit can make the power LED blink in S3. Change-Id: I2badc69510275df57938cb8607b3c4e0df50f028 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19ec/hp/kbc1126/acpi/battery.asl: Make \ISTR serializedIru Cai
This resolves the IASL remark: dsdt.aml 2141: Method (\ISTR, 2, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/21668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19util/cbfstool: calculate cbfs file size for xip stagesAaron Durbin
The initial lookup for cbfs location for xip stages is implicitly using the ELF size assuming it's relatively equivalent. However, if the ELF that is being converted contains debug information or other metadata then the location lookup can fail because the ELF is considerably bigger than the real footprint. BUG=b:70801221 Change-Id: I47024dcd8205a09885d3a3f76e255eb5e3c55d9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22936 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mainboard/lenovo: add Lenovo Z61t laptopAndrey Korolyov
This platform shares most hardware components with first-gen Core Lenovo laptops such as T60/X60, with much smaller EEPROM size as one of notable differences. The port features Intel graphics, ATI-based version should work with vendor VBIOS. Tested peripherals: - sleep/resume, - USB ports, - ACPI Fn key bindings/volume buttons, - backlight control, - ethernet, - wireless (under Linux), - sound/beep, - dock handling, - serial via dock. Untested peripherals: - IrDA, - parallel port, - PCMCIA, - S-Video port, - modem, - FP reader (should just work), - IEEE1394. Linux 3.16 works with native gfxinit perfectly, with Intel VBIOS console sometimes displays nothing when i915 framebuffer is used. Windows 7 has an interrupt assignment issue with iw3945, otherwise tested stuff is fine. Change-Id: I84c89cc47d3db126d827f92d50270954bc42f224 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/21019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19drivers/mrc_cache: only add mrc.cache when CACHE_MRC_SETTINGS is setIru Cai
In commit decd0628 (drivers/mrc_cache: move mrc_cache support to drivers) mrc.cache is always added, but CONFIG_MRC_SETTINGS_CACHE_SIZE is not used in Sandy Bridge, which makes mrc.cache have zero size and the machine will fail to boot after the first boot. Change-Id: Iab3ac87e43408ef51f0158f319eb1c8ccfce8a55 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/22925 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-19soc/amd/common/block/pci: Fix validation of pointerRichard Spiegel
Procedure write_pci_int_table() does not validates intr_data_ptr. It must be validated together with picr_data_ptr and idx_name. BUG=b:69868534 TEST=Build fake kahlee with intr_data_ptr not initialized, boot and see error message. Than build correct kahlee and verify that error message is gone. Change-Id: I5ee9a362600dbd6325254d7431172501181b52b0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-19soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused valueRichard Spiegel
In function load_smu_fw1(), variable base receives one value and is immediately overwritten. Remove the first line, as it's useless. This fixes CID 1383612 BUG=b:70620140 TEST=Build kahlee and boot. Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mainboard/intel/saddlebrook: add support for Saddle BrookTeo Boon Tiong
Add initial files to support the Saddle Brook board. This board uses the Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file. Most of the code has been taken carried over from kunimitsu with changes done for Saddle Brook. Saddle Brook is a reference board for Skylake SOC and has DDR4. TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully. Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Signed-off-by: Anuj Mittal <anujx.mittal@intel.com> Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/21436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-12-19nb/intel/nehalem/gma: Drop stale pre-pocessor guardsNico Huber
These were forgotten when updating the caller and resulted in build failures for every but the NGI path. Change-Id: I2490a3b4dca6c248eb37f43aa676ae619afdbfc7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-19mb/google/poppy: Configure WWAN gpiosFurquan Shaikh
BUG=b:70773281 Change-Id: If9b575568cabcbee03ad190b69d9c033890f7fa6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22927 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure GPP_B0 for WLAN wakeFurquan Shaikh
As per the latest schematics, this change configures GPP_B0 for WLAN wake and uses corresponding gpe bit in ACPI node for WLAN. This hasn't been tested yet. BUG=b:70775494 Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22928 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19mb/google/poppy: Configure pen reset and eject linesFurquan Shaikh
This change configures the GPIOs for pen reset and eject lines and exports required properties using ACPI table. BUG=b:70773138 Change-Id: I52f6c3dced54259cde8ee6753275622622e15954 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nautilus: Enable AER and LTR for root port 1Furquan Shaikh
Similar to other KBL projects, this change enables AER and LTR for root port 1 on poppy. BUG=b:65570878 Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_B8 for WLAN_PE_RSTFurquan Shaikh
BUG=b:62726961 Change-Id: I5a88e67d5a22f8a39427c95821ffee4f2fd717fa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix SATA configs againFurquan Shaikh
This change really fixes the SataMode to select non-RAID mode and enables SATA which was incorrectly disabled in a71276b (mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree). BUG=b:70160119 Change-Id: Ied6adabdc1d2458972bde628616a198cd41f9f3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy: Configure GPP_F3 as NCFurquan Shaikh
GPP_F3 is not connected on poppy or any of its variants. This change configures GPP_F3 as NC on poppy and all the variants. BUG=b:70160119 Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/poppy/variants/nami: Fix GPIO configuration for DEVSLPFurquan Shaikh
Nami uses DEVSLP1 and not DEVSLP0. This change updates the GPIO configuration for DEVSLP to match the latest version of schematics. BUG=b:70160119 Change-Id: Ifa181322011a4b8947ecd0fa44dcf790b0d8f657 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-19mb/google/fizz: Enable 2nd NIC ledsDavid Wu
This patch enables customized NIC leds as below: Green Orange (Amber) 100M off blinking 1000M on blinking BUG=b:69950854 TEST=Boot on fizz dut and observe the LEDs are behaving as expected. Perform suspend/resume test and the LEDs are still working as expected. Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/22817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-18amd/stoneyridge: Skip VGA initialization on S3 resumeMarshall Dawson
Sync with the other AMD implementations. Change-Id: I222cc7fcf5e58f451cee9621a1b876346226af09 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd/common: Factor out InitPost printed results to functionMarshall Dawson
Make a static function that can report the AmdInitPost() results. This makes it easier to keep lines within 80 columns. Clean up surrounding source. BUG=b:62240746 TEST=Build and boot Kahlee Change-Id: I6d288e76e7510528659436e61fdfa1d5db01f06c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-18soc/amd: Move stoneyridge features out of agesawrapperMarshall Dawson
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should it make any assumptions about the capabilities of a particular device. Move these into stoneyridge northbridge and southbridge files. BUG=b:70670425 TEST=Build and run Kahlee Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd/common: Remove #ifndef/#endif from AGESA wrapperMarshall Dawson
There isn't a good reason to keep the checks for __PRE_RAM__. The global variables are not used outside of ramstage and the linker removes them cleanly in other stages. BUG=b:70671590 TEST=Build and boot Kahlee Change-Id: I7a35141f212f340c157d57fde8daf93c0c383af8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-18soc/amd/common: Make AGESA event log parser staticMarshall Dawson
The function agesawrapper_readeventlog() is not used outside of the wrapper. Relocate it within the file and make it static. Change-Id: Ia7fefb4eadbace0cc2fb0f519a1acb7906baaf12 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-18soc/amd/common: Clean up AGESA event log functionMarshall Dawson
Clean up the source for agesawrapper_amdreadeventlog: * shorten the name to help keep lines within 80 columns * convert initializers to C99 * break the call from the callers' if() statements * streamline the printk formatting BUG=b:70671442 TEST=Build and run Kahlee, check console log Change-Id: I402c75e4d65a592b9d1557c5852df03e48e206b9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18drivers/mrc_cache: Add missing include file to mrc_cache.hMarshall Dawson
Add region.h for use by the struct region_device * in the mrc_cache_get_current() prototype. BUG=b:69614064 Change-Id: I940beac45eb43e804bc84fead7d5337a1c4e2ac1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-18spi/tpm: Clear pending irqs during tpm2_initShelley Chen
Seeing some instances were cr50 spi driver is starting a new transaction without getting a ready interrupt from cr50, which means that there are pending interrupts. Clearing these to be sure there are not any stale irqs for the next transaction. BUG=b:69567837 BRANCH=None TEST=run FAFT and see if any 0x2b recovery boots occur Change-Id: Ie099da9f2b3c4da417648ae10a5ba356b7a093ff Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-17drivers/mrc_cache: move mrc_cache support to driversAaron Durbin
There's nothing intel-specific about the current mrc_cache support. It's logic manages saving non-volatile areas into the boot media. Therefore, expose it to the rest of the system for any and all to use. BUG=b:69614064 Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 02:28:18 +0000