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2015-05-14lenovo: Disable radio when suspending or turning off.Vladimir Serbinenko
Without this some radios may remain operational. They may consume power but the immediate demonstrable effect is wireless LED still being on. Coreboot will reenable radios on resume or poweron. Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10190 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14x230: Fix VGA PCIIDs.Vladimir Serbinenko
x230 is ivy, not sandy. Fix copy-paste error. Change-Id: Ic462bab39ddac0e1e6fef1e043970957e45fb6ed Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10189 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-133rdparty/blobs: Move submodule marker forwardMarc Jones
Move the 3rdparty/blobs marker to include the following: a710941 amd/pi: Move AGESA cbfs access function to coreboot 63f1db5 AMD avalon: add PSP firmwares Change-Id: Ie12b273ab9d22ab440b477919e70419b21cb833b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10202 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13vboot: fix die() hang for recovery pathAaron Durbin
When we are taking the recovery path there is no slot or components to fill out. Change-Id: Ic97a247629365ef54a340c4398cb7491935edc11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10198 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-13amd/pi: Move AGESA cbfs access into the wrapperMarc Jones
The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10058 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13cbfstool: Don't typedef the comp_algo enumSol Boucher
Our style discourages unnecessary typedefs, and this one doesn't gain us anything, nor is it consistent with the surrounding code: there's a function pointer typedef'd nearby, but non-opaque structs aren't. BUG=chromium:482652 TEST=None BRANCH=None Change-Id: Ie7565240639e5b1aeebb08ea005099aaa3557a27 Signed-off-by: Sol Boucher <solb@chromium.org> Original-Change-Id: I4285e6b56f99b85b9684f2b98b35e9b35a6c4cb7 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13cbfstool: Support top-aligned addresses for new-format imagesSol Boucher
The cbfstool handling of new-style FMAP-driven "partitioned" images originally disallowed the use of x86-style top-aligned addresses with the add.* and layout actions because it wasn't obvious how they should work, especially since the normal addressing is done relative to each individual region for these types of images. Not surprisingly, however, the x86 portions of the build system make copious use of top-aligned addresses, so this allows their use with new images and specifies their behavior as being relative to the *image* end---not the region end---just as it is for legacy images. Change-Id: Icecc843f4f8b6bb52aa0ea16df771faa278228d2 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10136 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13cbfstool: New image format w/ required FMAP and w/o CBFS master headerSol Boucher
These new-style firmware images use the FMAP of the root of knowledge about their layout, which allows them to have sections containing raw data whose offset and size can easily be determined at runtime or when modifying or flashing the image. Furthermore, they can even have multiple CBFSes, each of which occupies a different FMAP region. It is assumed that the first entry of each CBFS, including the primary one, will be located right at the start of its region. This means that the bootblock needs to be moved into its own FMAP region, but makes the CBFS master header obsolete because, with the exception of the version and alignment, all its fields are redundant once its CBFS has an entry in the FMAP. The version code will be addressed in a future commit before the new format comes into use, while the alignment will just be defined to 64 bytes in both cbfstool and coreboot itself, since there's almost no reason to ever change it in practice. The version code field and all necessary coreboot changes will come separately. BUG=chromium:470407 TEST=Build panther and nyan_big coreboot.rom and image.bin images with and without this patch, diff their hexdumps, and note that no locations differ except for those that do between subsequent builds of the same codebase. Try working with new-style images: use fmaptool to produce an FMAP section from an fmd file having raw sections and multiple CBFSes, pass the resulting file to cbfstool create -M -F, then try printing its layout and CBFSes' contents, add and remove CBFS files, and read and write raw sections. BRANCH=None Change-Id: I7dd2578d2143d0cedd652fdba5b22221fcc2184a Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 8a670322297f83135b929a5b20ff2bd0e7d2abd3 Original-Change-Id: Ib86fb50edc66632f4e6f717909bbe4efb6c874e5 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10135 Tested-by: build bot (Jenkins)
2015-05-13secmon: allow for serial consoleAaron Durbin
Add necessary checks and objects for secmon serial console. Change-Id: Ibafa19061255ef6847a424922565a866328ff34c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10197 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13verstage: provide support for serial consoleAaron Durbin
verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13vboot: indicate verstage loading on consoleAaron Durbin
There was no indication of verstage being loaded. Provide this output so that one can follow the flow from console messages. Change-Id: I67ae6bb334608fe10a4a12fe690498afaf6b8366 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10195 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13console: enumerate all known stagesAaron Durbin
There are more stages than currently handled in the initial message from console_init(). Add support for those including an UNKNOWN catchall. Change-Id: I2374db590072bdca8ff35116e2ecb2ad6459b697 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10194 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13Include back the 306ax microcode again.Vladimir Serbinenko
In ee89435798022021026f511deddf0e3b401ad031 microcode for 306ax was forgotten in migration. Without microcode update my machine experiences random hangs and various misbehaviour. Change-Id: I61c704d88a8a0ed74a16fb3f80cce08e8515e6e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10180 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-05-13cbmem: Add initial allocation supportLee Leahy
Add support to allocate a region just below CBMEM root. This region is reserved for FSP 1.1 to use for its stack and variables. BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: I1d4b36ab366e6f8e036335c56c1756f2dfaab3f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10148 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13libpayload: x86: correct types used for IOAaron Durbin
libpayload on x86 defines u32 and uint32_t as typedefs of unsigned int. However, the readl/writel routines use long. With alias checking this throws type punning errors. Align the readl/writel/inl/outl types with the 32-bit fixed width ones that are exposed. Change-Id: Ie51cff8af4596948f6132e3cb743f1bc4ea8f204 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10186 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-13x86: expose tsc's timer_monotonic_get() in SMMAaron Durbin
The implementation of timer_monotonic_get() for the tsc module was being guarded from SMM. Allow this to be linked into SMM as the generic spi flash driver now needs this support which can be included in SMM. Change-Id: I3909edecac8de117922c4ea6c53e6e561f6f435b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10187 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13baytrail: broadwell: correct refcode loadingAaron Durbin
I messed up the conditionals on loading the reference code. The bug used || instead of && causing 2 reference codes to be loaded. Change-Id: I29a046bf0e8dc29a9efdb636ebfd04e11eb73f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10185 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-13vboot: handle RELOCATABLE_RAMSTAGEAaron Durbin
The support for RELOCATABLE_RAMSTAGE was accidentally omitted in the vboot loader. Add said support. Change-Id: I569918823253c33f698acefd6a619133543c7aef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10184 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-12FSP 1.1 Comparison BaseLee Leahy
Add FSP 1.0 source for comparison with FSP 1.1. BRANCH=none BUG=None TEST=None Change-Id: I8df349f97acfa74f4de3607d49633da3d4884546 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-12kconfig: properly build parser when LKC_GENPARSER=1Patrick Georgi
The rules didn't actually trigger to rebuild the parser. Change-Id: Id51aaa9816b069204c119622d60f7b728b762cad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10168 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-12libpayload: Fix passing BAR to EHCI driverPatrick Georgi
The EHCI driver never looked for the base address handed to it but instead used an uninitialized field for that information. Change-Id: I89fe0cc212092672b36e978083e3de78419b1eb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-12usbdebug: Add FTDI FT232H supportKyösti Mälkki
Tested with gizmosphere/gizmo1 Explorer add-on board, which exposes the following device: 0x0403 Future Technology Devices International, Ltd 0x6014 FT232H Single HS USB-UART/FIFO IC For now UART is hard-coded to 115200, 8n1, no flow-control. Change-Id: I4081f84f7700751ccbf079e7fcbb1467aa71d872 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10063 Tested-by: build bot (Jenkins)
2015-05-11vboot: allow for dynamic work buffersAaron Durbin
The vboot library currently relies on link-time known address and sizes of the work buffer. Not all platforms can provide such semantics. Therefore, add an option to use cbmem for the work buffer. This implies such platforms can only do verification of the firmware after main memory has been initialized. Change-Id: If0b0f6b2a187b5c1fb56af08b6cb384a935be096 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: add vb2_working_data_size()Aaron Durbin
Instead of using the symbols directly provide a size function to provide symmetry between getting the work data and size. It also allows for an abstraction where the linker symbols may not be the only source of this information. Change-Id: I4568064a0050d118c3544ab1ea59a08eb0bad8e4 Signed-off-by: Aaron Durbi <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11chromeos: remove vboot_verify_firmware()Aaron Durbin
vboot_verify_firmware() was only defined to ease upstreaming. It was only an empty inline as it is so remove it. Additionally, vboot2 does not require romstage_handoff so there's no need in adding it for the nyan boards. Change-Id: I4d84ac9fb60c756cf10742f26503f7f11af5f57b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: inject vboot loader for stage loadingAaron Durbin
As previously done the vboot loader can be optionally inserted in the stage loading logic in order to decide the source of each stage. This current patch allows for verstage to be loaded and interrogated for the source of all subsequent stages. Additionally, it's also possible to build this logic directly into one of the additional stages. Note that this patch does not allow x86 to work. Change-Id: Iece018f01b220720c2803dc73c60b2c080d637d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10154 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-11imd: don't recover on limit == 0Aaron Durbin
If the limit of the large starting region was set with a NULL pointer then the limit field will be 0. If the limit is zero then no attempt to recover is necessary as there is no region to recover. This prevented an early call cbmem_find() from hanging a rambi device. The config was with vboot enabled and was way before memory init in the sequence. Change-Id: I7163d93c31ecef2c108a6dde0206dc0b6f158b5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10175 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-11vboot2: Use the right set of compiler flags for building vboot librariesPatrick Georgi
This make it pass through -fno-stack-protector, and also uses libverstage fields consistently. verstage is for 'stage' stuff, libverstage for all the vboot logic. Change-Id: I3032e072414bed52effd2dc5057896781ad562c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10174 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-11vboot: allow options to be selected from .configAaron Durbin
In order to allow easier setting of variables without changing mainboards and/or chipset Kconfig files allow the vboot options to be selected by the user. Change-Id: I6e995eb209b4cd63c73ef679d0c5699759d129f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10153 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: fix vboot_reference compilationAaron Durbin
The VB_FIRMWARE_ARCH variable was not being set correctly, and the VBOOT_STARTS_IN_BOOTBLOCK Kconfig option was not properly prefixed with CONFIG_. Correct both of these oversights. Change-Id: Id27974c285d2629bd47b90b6a93aca1ec8a76512 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11chromeos: add missing vboot functionsAaron Durbin
Somewhere along the development path the following vboot functions were dropped: int vboot_enable_developer(void) int vboot_enable_recovery(void) Add them back, but also refactor the flag extraction so as not duplicate all that same logic. Change-Id: Id58f3b99f29caeff98b2d3111cfa28241d15b54f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11arm64: update verstage linkingAaron Durbin
The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Change-Id: Ib8427fe015b72e2282219f116a39949739a0af48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10150 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11arm: update verstage linkingAaron Durbin
The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Lastly, VERSTAGE_LIB has no value so remove it. Change-Id: Ie53b42c4995a96006463ec5b358aa43a731cb1b8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10149 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11cache: Add arch_program_segment_loaded call to arm and arm64Furquan Shaikh
arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. Use this function in rmodules as well instead of cache_sync_instructions which guarantees sync upto PoC. BUG=chrome-os-partner:37546 BRANCH=None TEST=Boots into depthcharge on foster Change-Id: I64c2dd5e40ea59fa31f300174ca0d0aebcf8041d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35ba0b882b86ff2c29ac766e1d65f403c8346247 Original-Change-Id: I964aa09f0cafdaab170606cd4b8f2e027698aee7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260908 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10173 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-11secmon: Add some missing filesPatrick Georgi
secmon is referring to uart's default_baudrate() and various coreboot version strings. Change-Id: I40a8d1979146058409a814d94ea24de83ee4d634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-11nvidia/tegra132: we write tables in ramstagePatrick Georgi
So that's more precise than "anything non-pre-ram". Change-Id: I21db536a5ea704c4b087f57d0b761dd3fdf43e3e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-11kconfig: handle globbed files backwardsPatrick Georgi
They're essentially collected on a stack before they're parsed. So we push them backwards, then parse them in the correct order. Change-Id: Ibf29559389cd19f260d67bae8e0b5ef9f4f58d91 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10169 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-10AGESA: Drop unused AGESA_MEM_TABLEKyösti Mälkki
These tables are not referenced anywhere, thus all comments about adjustments are void. Also drop stub AgesaReadSpd that is all commented out. Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-05-09cbfstool: fix 32bit host issuePatrick Georgi
Change-Id: Iaec748b4bdbb5da287520fbbd7c3794bf664eff6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10161 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sol Boucher <solb@chromium.org>
2015-05-09fmap: request libc compatibility level that includes memccpyPatrick Georgi
Change-Id: I928efe6f63305a0099d64e83091aa80768582f48 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10160 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-08cpu/amd/model_10xxx: Add missing ACPI _PSD objectTimothy Pearson
The ACPI power state generator for AMD 10xxx CPUs did not generate the _PSD object required for reliable PowerNow! operation. Without a correct _PSD object PowerNow! does not know the required core clock relationships, potentially causing unstable system operation. Generate the _PSD object in accordance with the BKDG Rev. 3.62. Change-Id: I255a4837ab29ff1b0874daf189ffb61798645795 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10142 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-08northbridge/intel/gm45/gma: Minor cleanupTimothy Pearson
1.) Removed invalid set of TRANS_STATE_MASK bit 2.) Used i915 register defines to clarify code Change-Id: I08d016e9d66b5eeea8f2174abaa35a98e2b4eca3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08southbridge/i82801gx: Add x_EN defines for LPC_ENDamien Zammit
A few hardcoded values could be fixed after this commit Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-08northbridge/intel/gm45/gma: Add backlight control register fieldTimothy Pearson
This allows the backlight control register to be set via devicetree.cb Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9330 Tested-by: build bot (Jenkins)
2015-05-08checkpatch: fine tune checksStefan Reinauer
Fine tune the following two checks: - Check for incorrect file permissions This one had a linux path hard coded, so it would choke on some commits unnecessarily. - FILE_PATH_CHANGES seems to not be working correctly. It will choke on added / deleted files even if the MAINTAINERS file is touched. Hence, switch from WARN to CHK (as WARN currently blocks commits as well) Change-Id: I9fccfbd75e94f420de45cf8b58071e3198065cf3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10123 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08fmaptool: Add listing of annotated CBFS sections and generate headerSol Boucher
The fmd compiler now processes "(CBFS)" annotations, distilling them into a comma-separated list of the names of sections containing CBFSes. This list is the only thing printed to standard output to enable easy capture and machine consumption by other tools. Additionally, the ability to generate a tiny header with a define for the primary CBFS's size is implemented and can be requested via a new command-line switch. Here's an example of how to use the new features: $ ./fmaptool -h layout.h layout_arm_8192.fmd layout.fmap 2>/dev/null FW_MAIN_A,FW_MAIN_B,COREBOOT The hypothetical fmd file contains three sections annotated as (CBFS), the names of which are printed to standard output. As before, a binary FMAP file named layout.fmap is created; however, because the command was invoked with -h, a header #define ing the offset of its FMAP section (i.e. where it will be relative to the base of flash once the boot image is assembled) is also generated. BUG=chromium:470407 TEST=Verify that fmd files without a "COREBOOT" section or with one that isn't annotated as "(CBFS)" are not accepted. Ensure that the list of CBFS sections matches the descriptor file's annotations and is led by the "COREBOOT" section. Invoke with the header generation switch and check that output file for reasonableness. BRANCH=None Change-Id: I496dd937f69467bfd9233c28df59c7608e89538f Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 9227698adecf675770b2983380eb570676c2b5d2 Original-Change-Id: I8b32f6ef19cabe2f6760106e676683c4565bbaad Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262956 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9967 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08fmaptool: Conform to cbfstool's error message formatSol Boucher
The tool now makes use of the ERROR() macros from common.h. Change-Id: Ie38f40c65f7b6d3bc2adb97e246224cd38d4cb99 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08cbfstool: Restructure around support for reading/writing portions of filesSol Boucher
The buffer API that cbfstool uses to read and write files only directly supports one-shot operations on whole files. This adds an intermediate partitioned_file module that sits on top of the buffer system and has an awareness of FMAP entries. It provides an easy way to get a buffer for an individual region of a larger image file based on FMAP section name, as well as incrementally write those smaller buffers back to the backing file at the appropriate offset. The module has two distinct modes of operation: - For new images whose layout is described exclusively by an FMAP section, all the aforementioned functionality will be available. - For images in the current format, where the CBFS master header serves as the root of knowledge of the image's size and layout, the module falls back to a legacy operation mode, where it only allows manipulation of the entire image as one unit, but exposes this support through the same interface by mapping the region named SECTION_NAME_PRIMARY_CBFS ("COREBOOT") to the whole file. The tool is presently only ported onto the new module running in legacy mode: higher-level support for true "partitioned" images will be forthcoming. However, as part of this change, the crusty cbfs_image_from_file() and cbfs_image_write_file() abstractions are removed and replaced with a single cbfs_image function, cbfs_image_from_buffer(), as well as centralized image reading/writing directly in cbfstool's main() function. This reduces the boilerplate required to implement each new action, makes the create action much more similar to the others, and will make implementing additional actions and adding in support for the new format much easier. BUG=chromium:470407 TEST=Build panther and nyan_big coreboot.rom images with and without this patch and diff their hexdumps. Ensure that no differences occur at different locations from the diffs between subsequent builds of an identical source tree. Then flash a full new build onto nyan_big and watch it boot normally. BRANCH=None Change-Id: I25578c7b223bc8434c3074cb0dd8894534f8c500 Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 7e1c96a48e7a27fc6b90289d35e6e169d5e7ad20 Original-Change-Id: Ia4a1a4c48df42b9ec2d6b9471b3a10eb7b24bb39 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265581 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10134 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08cbfstool: Add offset field to cbfstool directory's struct bufferSol Boucher
This allows calls to buffer_delete() to work on a buffer that has been buffer_seek()ed or the buffer created by a buffer_splice(). The same information could also be useful for other purposes, such as writing slices back to a file at the offset they originally occupied. BUG=chromium:470407 TEST=Attempt to perform the following sequence of buffer actions, then run it through valgrind to check for memory errors: for (int pos = 0; pos <= 3; ++pos) { struct buffer seek_test; buffer_create(&seek_test, 3, "seek_test"); if (pos == 0) { buffer_delete(&seek_test); continue; } buffer_seek(&seek_test, 1); if (pos == 1) { buffer_delete(&seek_test); continue; } buffer_seek(&seek_test, 1); if (pos == 2) { buffer_delete(&seek_test); continue; } buffer_seek(&seek_test, 1); if (pos == 3) { buffer_delete(&seek_test); continue; } } for (int pos = 0; pos <= 14; ++pos) { struct buffer slice_test; buffer_create(&slice_test, 3, "slice_test"); if (pos == 0) { buffer_delete(&slice_test); continue; } struct buffer sliced_once; buffer_splice(&sliced_once, &slice_test, 1, 2); if (pos == 1) { buffer_delete(&slice_test); continue; } if (pos == 2) { buffer_delete(&sliced_once); continue; } struct buffer sliced_twice; buffer_splice(&sliced_twice, &sliced_once, 2, 1); if (pos == 3) { buffer_delete(&slice_test); continue; } if (pos == 4) { buffer_delete(&sliced_once); continue; } if (pos == 5) { buffer_delete(&sliced_twice); continue; } struct buffer sliced_same; buffer_splice(&sliced_same, &slice_test, 1, 1); if (pos == 6) { buffer_delete(&slice_test); continue; } if (pos == 7) { buffer_delete(&sliced_once); continue; } if (pos == 8) { buffer_delete(&sliced_twice); continue; } if (pos == 9) { buffer_delete(&sliced_same); continue; } struct buffer sliced_thrice; buffer_splice(&sliced_thrice, &sliced_twice, 1, 0); if (pos == 10) { buffer_delete(&slice_test); continue; } if (pos == 11) { buffer_delete(&sliced_once); continue; } if (pos == 12) { buffer_delete(&sliced_twice); continue; } if (pos == 13) { buffer_delete(&sliced_same); continue; } if (pos == 14) { buffer_delete(&sliced_thrice); continue; } } BRANCH=None Change-Id: Id67734654a62302c0de37746d8a978d49b240505 Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 00c40982a21a91a488587dd3cead7109f3a30d98 Original-Change-Id: Ie99839d36500d3270e4924a3477e076a6d27ffc8 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/267467 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10133 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-08cbfstool: Simplify the common buffer_splice() function's interfaceSol Boucher
Previously, this function allowed one to pass a size of 0 in order to indicate that the entire buffer should be copied. However, the semantics of calling it this way were non-obvious: The desired behavior was clear when the offset was also 0, but what was the expected outcome when the offset was nonzero, since carrying over the original size in this case would be an error? In fact, it turns out that it always ignored the provided offset when the size was zero. This commit eliminates all special handling of 0; thus, the resulting buffer is exactly as large as requested, even if it's degenerate. Since the only consumer that actually called the function with a size of 0 was buffer_clone(), no other files required changes. Change-Id: I1baa5dbaa7ba5bd746e8b1e08816335183bd5d2d Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10132 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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