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2015-10-24intelvbttool: Add MakefilePaul Menzel
Add minimal Makefile based on cbmem’s Makefile. The make target `junit.xml` is removed as this is handled differently since commit de9adebb (Add junit.xml code to top Makefile.inc instead of utils). Also the `junit.xml` is removed in the make target `clean`. Additionally, the make target `distclean` is added, as the current junit.xml code in the top `Makefile.inc` requires that. Change-Id: I164b1f7733505bca6248d0711d7ad71d635fa926 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11876 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-10-24amd/agesa/hudson: Add support for hiding the USB1.1-only OHCITobias Diedrich
The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and (presumably) not used very often, add support for hiding it: 00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03) USB1 (3.0, XHCI) 00:10.1 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03) 00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB2 (2.0, OHCI+EHCI) 00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11) 00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB3 (2.0, OHCI+EHCI) 00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11) 00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB4 (1.1, OHCI only) Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7355 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24amd/sb800: Make UsbRxMode per-board customizableTobias Diedrich
On my Foxconn nT-A3500 on cold boot the board doesn't survive the soft reboot in the UsbRxMode path and the vendor bios doesn't touch this Cg2Pll voltage setting either. The fixup code for UsbRxMode in src/vendorcode/amd/cimx/sb800/SBPort.c doesn't seem to "CG PLL multiplier for USB Rx 1.1 mode", but rather lowers the Cg2Pll voltage from the hw default of 1.222V to 1.1V by setting Cg2Pll_IVR_TRIM in CGPllConfig5 to 1000. See also USB_PLL_Voltage which is only used in the UsbRxMode code path. However if this is already the efuse/eprom default for the SB800 then UsbRxMode is a no-op, so whether or not it gets executed depends on the very exact hw revision of the southbridge chip and could change between two instances of the same board. UsbRxMode used to be unitialized and was first set to default to 1 in http://review.coreboot.org/6474 (change I32237ff9, southbridge/amd/cimx/sb800: Uninitialized variables in config func): > > Why initialize those to 1? (just curious) > See src/vendorcode/amd/cimx/sb800/SBTYPE.h > git grep 'SbSpiSpeedSupport\|UsbRxMode' > src/vendorcode/amd/cimx/sb800/SBTYPE.h I could not find a corresponding errata in the SB800 errata list, however errata 15 (USB Resets Asynchronously With Port CF9h Hard Reset) might play into this being unsafe to do since the code uses CF9h to reset. So its possible that while previously undefined it still ended up defaulting to 0 and the codepath exercised on my board is simply buggy or there is a difference between a true "SB800" and the "A50 Hudson M1" presumably used on my board. Change-Id: I33f45925e222b86c0a97ece48f1ba97f6f878499 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10549 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-24amd/acpi: Clean up SMBus references.Tobias Diedrich
Replace the AMD SMBus section with the equivalent SB800 smbus.asl include or remove already commented-out sections. Verified by running the cpp preprocessor over the DSDTs and diffing the results against this patch. The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where someone added RADD and SADD to the OpRegion, but those are unused, so removing them is fine. Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10618 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-23google/auron: Remove additional SPD file entriesMarc Jones
Auron only has three GPIOs for RAMID, so there is no need for sixteen SPD file entries. Only include 8 SPD entries. Change-Id: Icf83719a2a5b9271b29f48cde5c66c4c8ccd07f4 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12073 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23Intel: Move MCRS ResourceTemplate outside of _CRS methodMartin Roth
On Broadwell, this reduces the number of 'remarks' in the IASL build from 222 to 3. Fixes these remarks: Object is not referenced (Name is within method [_CRS]) The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS ResourceTemplate when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying and can mask real issues. Moving the creation of the MCRS object to outside of the CRS method and referencing it from there solves this problem. This change was made for fsp_baytrail in commit 2eaa0d49 fsp_baytrail: Fix ACPI 'Object is not referenced' warnings Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23roda/rk9: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23lenovo/t400: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23lenovo/x200: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: I1e69cf0fd73e70ed6656b9ed6f55aba4c56a6edd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11882 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23southbridge/intel: Move `i82801gx/acpi/platform.asl` to `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact same ASL code though. So share this in the directory `src/southbridge/intel/common/acpi`. Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/cpu/intel/model_6dx/acpi`, although the devices can also use different Intel CPU models like, for example, `intel/model_6ex` on the Lenovo T60. Therefore move the file to the directory `src/cpu/intel/common/acpi` so that other devices, like Intel GM45 based devices, can also include it. Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23intel/fsp_baytrail: Fix logging of ISPEnable optionDavid Imhoff
Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP configuration option. TEST=Built and booted on Minnowboard Max Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-10-23asrock/e350m1: disable unconnected GPP PCIe clocksFelix Held
connections checked by desoldering the FCH and looking at the PCB this lowers the power consumption by about 150-200mW measured on primary side based on change #5397 Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/11866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-23cbfstool: Make sure fileno is available on CygwinStefan Reinauer
This patch fixes compilation of cbfstool on Cygwin. As reported in http://review.coreboot.org/#/c/10027 cbfstool on Cygwin likes to be compiled with -D_GNU_SOURCE. That patch was abandoned because it would unwantedly turn on more GNU extensions. Instead of doing that, only enable the define on Cygwin, switch to -std=gnu99 instead of -std=c99 to make fileno and strdup actually available. A MINGW32 check that was forgotten in Makefile was copied over from Makefile.inc to keep the two files in sync. This patch has no impact on non-Windows builds. Change-Id: I068b181d67daf9c7280110e64aefb634aa20c69b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11667 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-10-23SB800-mainboards: use write8 to disable unused GPP CLKFelix Held
don't use non-volatile pointers for MMIO access Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12081 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23superio/nuvoton/nct5572d: Enable power state after power failure supportTimothy Pearson
Change-Id: Ia0313b9ecd64c9e6f99a140772ebb35abe0175fd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11950 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23northbridge/amd/amdmct: Fix Family 15h detectionTimothy Pearson
Change-Id: I3623f8945bd62b7050ec609934f96543552c792b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12018 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-23southbridge/amd/sr5650: Fix GPP3a link training in higher width modesTimothy Pearson
Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11990 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-23device/hypertransport: Add additional debug outputTimothy Pearson
Change-Id: I94b870f47581a4a2591d02eeb37627666e0f4297 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11945 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2015-10-23cpu/amd/model_10xxx: Clean up debugging statementsTimothy Pearson
Change-Id: I6dff74b3857e1fb384aefc87b44e7679bd4aab07 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11948 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-23northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violationsTimothy Pearson
Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11942 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-23include/smbios: Update SMBIOS memory structures to version 2.8Timothy Pearson
Change-Id: Icda915933c4ebf3a735d9e1d4e4dbb1138a06b39 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11955 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins)
2015-10-23intel/cougar_canyon2: fix buildPatrick Georgi
The reintroduction of cougar_canyon2 crossed beams with the moving the GMA display brightness data in ACPI into individual mainboards. Make things build again by having the board use the same default values that it used to use automatically. They may be wrong, but no worse than what was there before. Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12132 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-23MAINTAINERS: Add script to test database and find maintainersStefan Reinauer
This utility should make it easier to complete and maintain the database of coreboot subsystem maintainers (MAINTAINERS file) This will need a bit of tender love and care to print information in an easily machine readable output for the build system, but its a first start to query the maintainers database. Build with: $ go build util/scripts/maintainers.go Find a maintainer for a set of files with: $ ./maintainers Makefile Makefile.inc Makefile is in subsystem BUILD SYSTEM Maintainers: [Patrick Georgi <patrick@georgi-clan.de>] Makefile.inc is in subsystem BUILD SYSTEM Maintainers: [Patrick Georgi <patrick@georgi-clan.de>] Check the maintainer database with: $ ./maintainers .gitignore has no subsystem defined in MAINTAINERS .gitmodules has no subsystem defined in MAINTAINERS .gitreview has no subsystem defined in MAINTAINERS 3rdparty/arm-trusted-firmware has no subsystem defined in MAINTAINERS 3rdparty/blobs has no subsystem defined in MAINTAINERS 3rdparty/vboot has no subsystem defined in MAINTAINERS COPYING has no subsystem defined in MAINTAINERS Documentation/AMD-S3.txt has no subsystem defined in MAINTAINERS Documentation/CorebootBuildingGuide.tex has no subsystem defined in MAINTAINERS Documentation/Doxyfile.coreboot has no subsystem defined in MAINTAINERS [..] Change-Id: I49c43911971152b0e4d626ccdeb33c088e362695 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12119 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-23northbridge/amd/amdfam10: Fix typo in commentTimothy Pearson
Change-Id: I0a9b3a66231052622c862bae32b900f52f6efba9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11944 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-23cbfstool: Fix tolower() calls on CygwinStefan Reinauer
Cygwin complains: cbfstool.c: 1075:5 error: array subscript has type 'char' [-Werror=char-subscripts] so add an explicit cast. Change-Id: Ie89153518d6af2bacce3f48fc7952fee17a688dd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11666 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-22allocator: Page align memory mapped PCI resourcesNico Huber
To help hypervisors to assign PCI devices individually to virtualization guests, page align dynamically allocated MMIO resources. Tested with kontron/ktqm77 which has dynamically configured onboard devices on the root bus and secondary buses. Booted Linux and checked the configuration with `lspci -v`. Got the configuration through Muen's tools which are very picky about overlapping and alignment. Booted a Muen based system that uses many onboard devices. GMA, xHCI and one NIC (on a secondary bus) were verified to function properly. Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12111 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-22cbfstool/Makefile: Also rm fmd_(parser|scanner).[ch] in cleanNico Huber
Change-Id: I783aa4b2319aaedd57ce9a67ca935392a611298f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12127 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22cbfstool/Makefile: Drop unused, irritating definition of `obj`Nico Huber
Change-Id: Id8dda8a973dcf991ac494c2d50258d1b51e43c6a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22gma ACPI: Make brightness levels a per board settingNico Huber
Those are actually board specific. Keep the old value as defaults, though. The defaults are included by all affected boards. Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11705 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-22model_fxx/powernow: add dual core Socket F TDPsJonathan A. Kollasch
Values based on correlation of brand strings, brand numbers and the TDP listings on AMD's web site (Wikipedia for Athlon 64 FX-7x TDPs). Change-Id: I7e6d12d0b6cc4fefc3f84076234c62c40e08304c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10926 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
Please don't remove chipsets and mainboards without discussion and input from the owners. Someone was asking about cougar canyon 2 just a couple of weeks ago - there's obviously still interest. This reverts commit fb50124d22014742b6990a95df87a7a828e891b6. Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/12128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-22MAINTAINERS: Fix format for file entries (F:)Stefan Reinauer
According to the documentation further up in the file: F: drivers/net/ all files in and below drivers/net F: drivers/net/* all files in drivers/net, but not below F: */net/* all files in "any top level directory"/net Add trailing slashes to directory names. Change-Id: I7bfd2eb2528a75fb6af79a990acb89f5e4251383 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12118 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-20libpayload: Add ptrdiff_t typedefPatrick Georgi
vboot2 in payloads (eg depthcharge) needs it. Change-Id: I4e79ae29cc282c8680f21686befd35c4ff461b3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11922 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-20Enable MULTIPLE_CBFS_INSTANCES on x86, tooPatrick Georgi
It works there, we want it, disable that restriction. Change-Id: Idc023775f0750c980c989bff10486550e4ad1374 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/12094 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-20Revert "coreboot_table: don't add CMOS checksum twice."Nico Huber
This reverts commit e6606518243d9beda31693d40493b5f7a1a3e2e0. After some discussion on IRC we decided to revert it as libpayload can only read the copy that was removed (and other users like nvramtool can only read the other copy). So we need both copies at this time. Signed-off-by: Nico Huber <nico.h@gmx.de> Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db Reviewed-on: http://review.coreboot.org/11696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-19cbfstool: Fix typo in error messagePatrick Georgi
Change-Id: Iaee7e2c74fe9f63d4d4878278bd445af393942f4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11920 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-19vendorcode/google: Deal with MULTIPLE_CBFS_INSTANCESPatrick Georgi
We need to special-case filling out the vboot structures when we use CBFS instead of vboot's custom indexed format, otherwise (due to the way the CBFS header looks), it will try to write several million entries. Change-Id: Ie1289d4a19060bac48089ff70e5cfc04a2de373f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/11914 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-18Makefile.inc: Put every tool in `TOOLLIST` on separate linePaul Menzel
This way, commit differences will be easier to read. Also sort the list lexicographically. Change-Id: I4ce3ac9018a3fddf5e30d7c1ac0c57090fac1d3d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12084 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-17armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/writePaul Kocialkowski
Some registers only allow word-sized or half-word-sized operations and will cause a data fault when accessed with byte-sized operations. However, the compiler may or may not break such an operation into smaller (byte-sized) chunks. Thus, we need to reliably perform word-sized operations for 32 bit read/write and half-word-sized operations for 16 bit read/write. This is particularly the case on the rk3288 SRAM registers, where the watchdog tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the compiler, where a 32 bit read would be broken into byte-sized chunks, which caused a data fault when accessing the watchdog tombstone register. The definitions for byte-sized memory operations are also adapted to stay consistent with the rest. Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11698 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-17cbfstool: Fix removing and adding file with same nameAaron Durbin
Currently, cbfstool regressed that removing a file from CBFS the space is marked as empty but the filename is still shown, preventing adding a file with the same name again. [1] ``` $ echo a > a $ echo b > b $ ./util/cbfstool/cbfstool test.rom create -m x86 -s 1024 Created CBFS (capacity = 920 bytes) $ ./util/cbfstool/cbfstool test.rom add -f a -n a -t raw $ ./util/cbfstool/cbfstool test.rom add -f b -n b -t raw $ cp test.rom test.rom.original $ ./util/cbfstool/cbfstool test.rom remove -n $ diff -up <(hexdump -C test.rom.original) <(hexdump -C test.rom) --- /dev/fd/63 2015-08-07 08:43:42.118430961 -0500 +++ /dev/fd/62 2015-08-07 08:43:42.114430961 -0500 @@ -1,4 +1,4 @@ -00000000 4c 41 52 43 48 49 56 45 00 00 00 02 00 00 00 50 |LARCHIVE.......P| +00000000 4c 41 52 43 48 49 56 45 00 00 00 02 ff ff ff ff |LARCHIVE........| 00000010 00 00 00 00 00 00 00 28 61 00 00 00 00 00 00 00 |.......(a.......| 00000020 00 00 00 00 00 00 00 00 61 0a ff ff ff ff ff ff |........a.......| 00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| $ ./util/cbfstool/cbfstool test.rom add -f c -n c -t raw $ ./util/cbfstool/cbfstool test.rom print test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0 alignment: 64 bytes, architecture: x86 Name Offset Type Size c 0x0 raw 2 b 0x40 raw 2 (empty) 0x80 null 792 ``` So it is “deteled” as the type changed. But the name was not changed to match the *(empty)* heuristic. So also adapt the name when removing a file by writing a null byte to the beginning of the name, so that the heuristic works. (Though remove doesn't really clear contents.) ``` $ ./util/cbfstool/cbfstool test.rom remove -n c $ ./util/cbfstool/cbfstool test.rom print test.rom: 1 kB, bootblocksize 0, romsize 1024, offset 0x0 alignment: 64 bytes, architecture: x86 Name Offset Type Size (empty) 0x0 null 2 b 0x40 raw 2 (empty) 0x80 null 792 ``` [1] http://www.coreboot.org/pipermail/coreboot/2015-August/080201.html Change-Id: I033456ab10e3e1b402ac2374f3a887cefd3e5abf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11632 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-10-17cbfstool/cbfs_image.c: Just use one space before `=`Paul Menzel
Change-Id: Id31c889d1e83e7ddfb0f0f98b78601f37b71cfa2 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17coreinfo: reboot when finishedMaxime de Roucy
Behave as nvramcui. Avoid a "General Protection Fault Exception" when launched by SeaBIOS on pcengines APU1. Change-Id: I00b1f859f76e693e8d49a38c1e02f4f49add85b7 Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com> Reviewed-on: http://review.coreboot.org/11731 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17libpayload/Kconfig: Use official spelling for TinyCursesPaul Menzel
TinyCursess is officially spelled in CamelCase [1]. [1] https://github.com/tommyettinger/TinyCurses Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11727 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17libpayload/configs: Add default configuration with TinyCurses enabledPaul Menzel
Change-Id: Ib057e2b5f15b8d5bcdf45666f8761614317d25ee Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11726 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17Add junit.xml code to top Makefile.inc instead of utilsMartin Roth
Instead of adding code to generate the junit.xml file for jenkins to each of the util makefiles, add it once to the top level Makefile.inc. Create a list of tools to run the test on. Add nvramtool and inteltool to the list of utilities tested. Note that the util builds depend on implicit rules, so MFLAGS and MAKEFLAGS have to be cleared to get the builds to work. Change-Id: Id7ee5ea41ce3bf4a40fb50942ae785bb838fa639 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11910 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17kontron/ktqm77: Tag all four USB3 ports switchable and SS capableNico Huber
With the introduction of these options in commit b26156e (bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.) the default regressed to disable these capabilities. Maybe other boards regressed too. I didn't check. Change-Id: I220896e656d00145618e61d55b74904517c7d855 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11287 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17enable lint-stable build on jenkinsMartin Roth
This will run the lint-stable scripts on jenkins to block a commit with obvious and known errors. It runs in under a second on my system, so shouldn't contribute to any real delay on jenkins. Change-Id: I6ff3468ec29dc4ccd0c115f2c26e26b291c507df Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11892 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-17lint: Fix shellcheck warnings, add commentsMartin Roth
When the script was pulled out of the makefile, it was left as it was written in the makefile to show the continuity with the original. This patch cleans up issues identified by shellcheck and adds comments. Change-Id: I5e6573a4fdfbb397e15db38e2e3dfadeb3430573 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17lint: Add junit.xml output for jenkinsMartin Roth
To add lint to jenkins testing, we need junit.xml output. This adds an optional --junit command line parameter to enable output to an xml file in the lint directory. Change-Id: I5588190cb050b9dbe99458cb18a71a147769f50e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11891 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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