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2020-09-30drivers/pc80/rtc: Fix linking verstage (and use `all` target)Nico Huber
`option.c` was already linked into verstage but needs `mc146818rtc.c` to work. While we are at it, also make use of the `all` target. Change-Id: I8f545e036962ed0716bcd3b9a5b5d06e18a367f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45802 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/icelake/acpi/gpio.asl: Correct GADD methodAngel Pons
Some cases are inconsistent. Refer to the 495 series on-package PCH to confirm which GPIO pads are the first for each community and fix it. Change-Id: Ie4c4c12c6629478d754f55fa3fb75fa16eb01335 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30lenovo/t440p: Add HDA verbs from the OEM firmwareIru Cai
To get the HDA verbs from the OEM firmware, open the firmware with UEFITool, search for the existing HDA verbs, extract the UEFI module and look for the verbs. Copy the consecutive 4 dword sets that look like HDA verbs. It is tested to make audio output from both the speaker and headphone work. Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30mb/packardbell/ms2290/acpi: Convert 'battery.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Id8b7d3776ab2cc8c487095273582cd013241bd3a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30mb/packardbell/ms2290/acpi/battery.asl: Remove unused remainderElyes HAOUAS
We store the remainder in Local0, but we never use it. Change-Id: I4d209d7434508cb626aca8e7df50cc1c424e294a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30soc/intel/skylake: Move PMC MMIO offset macro into pmc.hSubrata Banik
This patch ensures PMC offset 0xfc resides into pmc.h rather defining into p2sb.h. Change-Id: Iae1c38beae15355a077be80112b723b8ad3d0a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45800 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/skylake: Align PMC offset 0x31C name with CNLSubrata Banik
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename CIR31C with CPPMVRIC. Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/skylake: Align soc_pch_pirq_init() with CNLSubrata Banik
This patch replaces pch_interrupt_routing[] with PCH_IRQx macro. Change-Id: I9645b0e185bcde7b27da35863564dbcf73850e8c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45788 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/intel/apollolake: Add PCH_IRQx into irq.hSubrata Banik
This patch is needed to make use of LPC common code. Change-Id: I5d0e8dbf8f8e52caf4ba78c0e3969efaac387204 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-30mb/google/puff: Update DPTF parameters for faffyDavid Wu
1. TSRO trip point from 75C change to 73C 2. Sample period time from 5s change to 60s BUG=b:160385395 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-09-29mb/google/volteer: Change default camera power GPIO to 0Daniel Kang
The default GPIO values for camera power were set as 1 so the LED was turned on by default when the board is powered on. This status is kept until the camera is probed then being turned off. So the LED is turned on for a few seconds during the boot up. By setting the default power to 0, the LED is lit only when camera is turned on for probing and this should be just a blink. BUG=b:167635396 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check it is not lit more than 0.5 seconds. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ic7df391aa512daafe6e1ce49e9222b90e17ad806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45058 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29mb/google/volteer/halvor: Update settings for audio functionFrank Wu
Configure overridetree settings for audio function. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-29mb/google/volteer: Add "i2c-allow-low-power-probe" property forDaniel Kang
cameras There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c device can support driver probe without power up the device. In order to support this, need add coreboot add "i2c-allow-low-power-probe" property. BUG=b:169058784 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check it blinks. It should not blink. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-09-29cpu/qemu-x86/car: Move long mode entry right before c entryPatrick Rudolph
This fixes non-emulation platforms as those are using 32bit code after the bootblock_crt0 entry, like setting up CAR and updating microcode, which isn't yet converted to support long mode. This is a noop for the only supported x86_64 platform and all x86_32 platforms. Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29soc/intel/jasperlake: Add IGD, MCH Device IDKrishna Prasad Bhat
Add IGD Device ID and MCH Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: I00ee7950ffa378b428a76bf367a9a05ab287e7ed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29mb/clevo/cml-u: drop PcieRpSlotImplemented for card readerMichael Niewöhner
PcieRpSlotImplemented should only be set to 1 for PCIe ports implementing a PCIe slot. Drop it for the on-board card reader. Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29nb/intel/gm45: Answer question about conversion stepping A1Angel Pons
The datasheet briefly mentions what this mysterious stepping is about. Change-Id: I5bc1040b74fcdf3822b15e7564f8e4ccebd7d45f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45449 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29cpu/x86/smm/smihandler.c: Implement smm_get_save_state()Arthur Heymans
This will be used in common save_state handling code. Change-Id: I4cb3180ec565cee931606e8a8f55b78fdb8932ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29cpu/x86/smm/smmhandler.c: Get revision using C codeArthur Heymans
This allows to remove some assembly code. Tested with QEMU Q35 to still print the revision correctly. Change-Id: I36fb0e8bb1f46806b11ef8102ce74c0d10fd3927 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-29mb/intel/jslrvp: Update PMC as hidden deviceMaulik V Vaghela
This change allows treating the PMC as a 'hidden' PCI device on JasperLake, so that the MMIO & I/O resources can be exposed as belonging to this device, instead of the system agent and LPC/eSPI. Original patch for jasperlake SoC here: CB:42018 This change was missing for JasperLake rvp board. TEST=Checked PMC init function is called and also checked PCI resource for PMC device 1f.2. Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-29soc/intel/common: Add config option to enable TME/MKTMEPratik Prajapati
Add config option to enable TME/MKTME. The spec is available at: "https://software.intel.com/sites/ default/files/managed/a5/16/Multi-Key-Total-Memory-Encryption- Spec.pdf" Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I181aed2bf4a79005fe42e3e133b5faee91201dad Reviewed-on: https://review.coreboot.org/c/coreboot/+/45087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-28util/intelp2m/apl: Remove unused plat-spec functionMaxim Polyakov
Change-Id: I42074387a08b66b038ad2939f31be263eaa3af0e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44473 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/fizz/endeavour/gpio: Reflow long linesMaxim Polyakov
Use the 96 character limit. Change-Id: I865288051869e50602a579a6999b1b23ef68ec2f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28Revert "soc/intel/xeon_sp: Improve performance efficiencies"Subrata Banik
This reverts commit d51449d017410fedb55e93f71fb322749ba888b5. Reason for revert: Causing compilation issue as below src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa': src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] &hob->PlatformData.IIO_resource[socket]; ^ Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28Intel GBE 82579LM bincfg set and specTom Hiller
Using bincfg, generate Intel 82579LM GBE region firmware. * Intel 82579LM is used in Lenovo models including x220 and x230. * PXE is disabled. * Intel 82579V variant could be generated with a few modifications to set. Noted in set file comments. Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28util/intelp2m: Remove unnecessary tabsMaxim Polyakov
Change-Id: I5aa4b9ac4fa1ceb6f3c2ade214d47b29246ece55 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-28mb/google/octopus/variants/fleex: Only do LTE power off for LTE skuEric Lai
Only do LTE power off for LTE sku in order to save extra 130ms delay for non-LTE sku. BUG=b:168075958 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If983185ff2f09fb1b2553c6ff1a1473d3254de4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/45687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-09-28mb/clevo/cml-u/Kconfig: Remove MAINBOARD_SMBIOS_PRODUCT_NAMEElyes HAOUAS
MAINBOARD_SMBIOS_PRODUCT_NAME is duplicated. Change-Id: I011f83c4d4e0657256839db207bfd1517922744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-28soc/amd/picasso: Set eMMC preset UPDsRaul E Rangel
Now that all boards have bootable driver strengths and init frequency, we can pass them to FSP. BUG=b:159823235 TEST=Boot ezkinil to kernel and print presets. SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x3ff: SdClkFreq SDHC0x8F2 Default Speed 3.3V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8F4 High Speed 3.3V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8F6 SDR12 1.8V => 0x0008 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x8: SdClkFreq SDHC0x8F8 SDR25 1.8V => 0x0004 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x4: SdClkFreq SDHC0x8FA SDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x8FC SDR104 1.8V => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq SDHC0x8FE DDR50 1.8V => 0x0002 14 => 0 [B]: DvrStrength 10 => 0: ClkGen 00 => 0x2: SdClkFreq SDHC0x900 HS400 => 0x4000 14 => 0x1 [A]: DvrStrength 10 => 0: ClkGen 00 => 0: SdClkFreq Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28mb/google/zork: Set eMMC presetsRaul E Rangel
They should be tuned per board to get the best signal and boot time. This fixes the HS400 preset, so it's correctly set to A. It also changes the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is set to A. I chose 1 as the init kHz value since that's what depthcharge uses to calculate the init clock. BUG=b:159823235 TEST=Boot Ezkinil and dump SDHCI preset registers. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28soc/amd/picasso: Add eMMC driver strength and init kHz settingsRaul E Rangel
This allows passing in the presets to FSP. I will set the UPD values after all the zork boards have had their presets correctly set. This way we don't override the UPD defaults with 0s. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-28mb/ocp/deltalake: add LPC device entry in ACPIJonathan Zhang
PCH LPC device is on CSTACK. Add LPC ACPI device entry. Without this change, following error message shows up in target OS boot log: ACPI BIOS Error (bug): Failure looking up [\_SB.PCI0.LPCB], AE_NOT_FOUND (20180105/dswload-211) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20180105/psobject-252) ACPI Error: AE_NOT_FOUND, (SSDT:COREBOOT) while loading table (20180105/tbxfload-228) ACPI Error: 1 table load failures, 1 successful (20180105/tbxfload-246) Also TPM device is not created. TESTED=Booted DeltaLake DVT, run following command in target OS: [root@dhcp-100-96-192-153 ~]# dmesg | grep tpm [ 7.331890] tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 16) Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I8614f6951389bd5c8f8f33522d0a9a9160ac3f66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-09-28soc/intel/xeon_sp/cpx: add ACPI name for CSTACKJonathan Zhang
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table generated. The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment does not support multiple PCIe stacks, eg. IIO stacks. For now, assign the name to PCIe domain. In future, the name needs to be assigned to CSTACK. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I24a6f29734452426218419cdcf66702edde96f46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-28soc/intel/common/block/lpc: add acpi nameJonathan Zhang
Add ACPI name for LPC device. The name matches with what is in soc/intel/common/block/acpi/acpi/lpc.asl. Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC, remove duplicated acpi name assignments. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28doc/mb/ocp: update deltalake server documentationJonathan Zhang
Upon completion of 2nd build/test/release cycle of Deltalake server alternative firmware engineering, update the document. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP releaseJonathan Zhang
Intel CPX-SP FSP ww38 release made some changes to FSP-M header file. Those changes do not need corresponding soc code change. TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake DVT to target OS. Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/octopus/var/fleex: Use Wifi SAR table for non-LTE sku onlyEric Lai
Use Wifi SAR table for non-LTE sku only. BUG=b:169115341 BRANCH=octopus TEST=Check no SAR table can be loaded with sku id 4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I086fa14a9f23e4a0fc0ef8085040219c932dbf17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45640 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28include/cpu/x86/tsc: Fix rdtsc on x86_64Patrick Rudolph
The used assembler code only works on x86_32, but not on x86_64. Use the inline functions to provide valid rdtsc readings on both x86_32 and x86_64. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: Icf706d6fb751372651e5e56d1856ddad688d9fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-09-28arch/x86/smbios: Add SMBIOS Thread CountFrancois Toguo
Add Thread Count in SMBIOS type 4 "Processor Information". Modify Thread Count 2 according to SMBIOS spec, it should be the number of threads per processor socket. TEST="dmidecode -t4" to check. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/volteer: Use Genesys Logic GL9755 for Delbin, Volteer2Ravi Sarawadi
Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755 for Delbin and Volteer2. BUG=b:166141961 TEST=Boot to kernel on Delbin, Volteer2 boards. Check PC10 in IDON. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45708 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28arch/x86/Kconfig: Move pagetables down by 4KPatrick Rudolph
In case of 64K bootblock the pagetables don't fit, as the CBFS header also needs a few bytes. Fixes build error on platforms that use 64KiB bootblock. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37394 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/purism/librem_whl: Drop 3Gbps SATA limit; enable and set SATA tuning paramsMatt DeVillier
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this, so limiting SATA speeds to 3Gbps is no longer needed. Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/purism/librem_skl: Enable and set SATA tuning paramsMatt DeVillier
Some Librems have issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this. Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7 Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5nick_xr_chen
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2 BUG=b:168564129 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-09-28mb/google/volteer/var/terrador: Enable audio SMBIOS OEM stringKevin Cheng
It needs to use probe statement in overridetree.cb to enable the cache of fw_config field implemented by cb:44782 and cb:44783. BUG=b:161963281 TEST= dmidecode -t 11 shows correct audio fw_config. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4 Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28mb/google/zork: update telemetry settings for berknipKevin Chiu
update telemetry to improve the performance. BUG=b:168581158 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test Change-Id: Ib93905cd89132664b06f2476e94494e96980642c Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-28Documentation/mainboard: Add Missing OCP Delta Lake LinkChristian Walter
Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28mb/google/dedede/var/magolor: apply DPTF settingRen Kuo
add tcc, critical, passive policy, and pl values from thermal team BUG=b:168353037 TEST=build and verify by thermal tool Change-Id: I887d494ff097a881d519a456f24578a278323051 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45453 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/dedede/var/magolor: Add ACPI camera supportRen Kuo
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM0 in devicetree BUG=b:166527568 TEST= build and verify function by cam ap on DUT Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Ica6aa8ddc03a1dab5b548a759825dd3a4de3101f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45329 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/dedede/var/madoo: Clean-up static camera ASL fileKarthikeyan Ramasubramanian
Camera ACPI tables are generated at run-time for all variants of Dedede. BUG=None TEST=Build madoo variant. Change-Id: Icb74c01a0a6dbc620466b64cd2b5652408ca41b9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-13 03:34:43 +0000