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2013-01-12Implement GCC code coverage analysisStefan Reinauer
In order to provide some insight on what code is executed during coreboot's run time and how well our test scenarios work, this adds code coverage support to coreboot's ram stage. This should be easily adaptable for payloads, and maybe even romstage. See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for more information. To instrument coreboot, select CONFIG_COVERAGE ("Code coverage support") in Kconfig, and recompile coreboot. coreboot will then store its code coverage information into CBMEM, if possible. Then, run "cbmem -CV" as root on the target system running the instrumented coreboot binary. This will create a whole bunch of .gcda files that contain coverage information. Tar them up, copy them to your build system machine, and untar them. Then you can use your favorite coverage utility (gcov, lcov, ...) to visualize code coverage. For a sneak peak of what will expect you, please take a look at http://www.coreboot.org/~stepan/coreboot-coverage/ Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2052 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12No random directoriesStefan Reinauer
Please, don't just add random directories for a single file because it seems convenient. There already is a chromeos directory, that should be used. Change-Id: I625292cac4cbffe31ff3e3d952b11cd82e4b151e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2137 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12Move init.S to a proper filenameRonald G. Minnich
Also, remove unnecessary junk and prepare for future build changes. Change-Id: I143777ec7e67ea4d6fed00084aafcb94c7866b4d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2141 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-01-11Fix console.c with serial support disabledStefan Reinauer
During the ARM port, disabling serial console became broken. This patch fixes it. Change-Id: I40460596073918a08c19bb9c991cada341cca940 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2136 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11cbmem: replace pointer type by uint64_tStefan Reinauer
Since coreboot is compiled into 32bit code, and userspace might be 32 or 64bit, putting a pointer into the coreboot table is not viable. Instead, use a uint64_t, which is always big enough for a pointer, even if we decide to move to a 64bit coreboot at some point. Change-Id: Ic974cdcbc9b95126dd1e07125f3e9dce104545f5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2135 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11armv7: Add temporary build script for CrOS devsDavid Hendricks
This build script will: - Build coreboot.rom - Download BL1, extract and place it if necessary - Do a partial flash via Servo, using some flashrom trickery to make the process fast. This probably should not be submitted, unless the intention is to back it out eventually. Credit goes to Hung-Te for writing the original version. Change-Id: Ia7a4bea6077416fc06768a5de5ee07edc973ede2 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2134 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11exynos5250: Hacked up lowlevel_init_cDavid Hendricks
This is the first lowlevel init routine that gets called in romstage. It's fugly and needs a lot of clean-up, but does the job for now. Change-Id: Id54bf4f1c3753bcbed5f6b5eeb4b48bc3b41ce93 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2133 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-11exynos5250: Temporarily remove intermediate rule in MakefileDavid Hendricks
This cannot be used until we get the BL1 mess sorted out. Change-Id: I2490addb31256e27caa89ebb5b1501296e6903bd Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-11AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITSZheng Bao
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-10armv7: replace magic constant for romstage locationDavid Hendricks
This replaces 0x02023400 with an SoC-specific Kconfig variable. Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10add a few entries to .gitignoreDavid Hendricks
- Development friendly files (tags, clang_complete) - Cross-compile stuff (xgcc, tarballs) This patch was originally written by Stefan. Change-Id: I4229414c94ee04a4f38a748369c4ac90fda57aea Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/2128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-10armv7: add *(.data) back into .romdata sectionDavid Hendricks
This doesn't seem to be strictly required (so far), but makes sense. Change-Id: I18416c427ff886507ae09c7fc1a018baf94af24a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2131 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: update board_init_f function signatureDavid Hendricks
We don't pass arguments when we jump out of assembly code. Change-Id: Iccf3a6f713e260b08f9ff47e8b542b9e96369166 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: dynamically calculate the branch offset in cbfstoolDavid Hendricks
This tidies up the ARMV7 case when creating cbfs: - Calculate the offset using the size of the master header and offsets rather than using a magic constant. - Re-order some assignments so things happen in a logical order. Change-Id: Id9cdbc3389c8bb504fa99436c9771936cc4c1c23 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2125 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10armv7: delete some unused filesDavid Hendricks
Change-Id: I4601b97cbd7dbfb6ee742b3920d2aac4ac49b958 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2121 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-01-10snow: add max77686 driver in romstage and ramstageDavid Hendricks
Change-Id: Id3e20b1ab5d85cfd22e2dae2750f32007b7f8f74 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2123 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10exynos5250: clean-ups for clock_initDavid Hendricks
This does some clean-up for the exynos5250 clock_init.c: - No global data. - Remove some unused #includes - Hard-code the memory type for Elpida DRAM. This will need to be fixed eventually (or the system will be unstable), but is good enough for early bring-up and until we finish other re-factoring. Change-Id: Icd2cf8ba35058cbd1131666db311dfb77ef1a160 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2127 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10exynos5250: un-comment a lot of code which was left out earlierDavid Hendricks
Turns out initializing power rails is necessary, even for getting serial output. Change-Id: I3042c1001ae43b1e793ee6cb90bb79b8db0f8fd1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2126 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10size optimizations for max77686David Hendricks
This contains some size optimizations for the Maxim MAX77686 driver: - change max77686_para.vol_{min,div} from u32 to u16 (currently their max value is 50000 so it should be fine) - remove max77686_para.regnum which takes 4 bytes for each and is not used (Patch was originally written by Hung-Te Lin, I'm just uploading it) Change-Id: I24044427c49467e99380d1f60ebc59e69c285b22 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2124 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10Fix 2 infinite loops if IMC doesn't respondMartin Roth
ACPI code: The ACPI code is not currently being compiled in by default, but assuming that it will be at some point, I'm fixing the loop that waits for the IMC to respond after sending it a command. The loop now exits after 500ms, similar to the function in agesa. Agesa Code: a 16 bit variable will always be less than 100000. Change to be a 32 bit variable. Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-09Fix typo in SB800 Kconfig for IMC positionMartin Roth
The cimx/sb800 IMC Firmware location Kconfig option has a typo which would could set it to the wrong location. Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-08qemu-x86: Implement more featuresStefan Reinauer
This patch switches the Qemu target to use (pseudo) Cache As RAM and enables some ACPI code. This allows to use the CBMEM console and timestamp code with coreboot in Qemu. Right now, the ACPI code is commented out because leaving it in breaks IDE. Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2113 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08cbmem utility: Find actual CBMEM areaStefan Reinauer
... without the need for a coreboot table entry for each of them. Change-Id: I2917710fb9d00c4533d81331a362bf0c40a30353 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2117 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08cbmem utility: unify debug outputStefan Reinauer
... and indent it to make output more comprehensible. Change-Id: If321f3233b31be14b2723175b781e5dd60dd72b6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2116 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-08cbfstool: index is replaced by strchr.zbao
From index(3): CONFORMING TO 4.3BSD; marked as LEGACY in POSIX.1-2001. POSIX.1-2008 removes the specifications of index() and rindex(), recommending strchr(3) and strrchr(3) instead. Change-Id: I3899b9ca9196dbbf2d147a38dacd7e742a3873fe Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-08cbmem utility: Add option to dump cbmem consoleStefan Reinauer
This adds an option to the cbmem utility to dump the cbmem console. To keep the utility backwards compatible, specifying -c disables printing of time stamps. To print both console and time stamps, run the utility with -ct Change-Id: Idd2dbf32c3c44f857c2f41e6c817c5ab13155d6f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2114 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2013-01-08cbmem utility: drop obsolete python based implementationStefan Reinauer
The first version of the cbmem utility was written in python, but it had issues with 64bit systems and other little hick ups. Since the C version has much fewer dependencies (no python needed on target system), and it works in all corner cases, drop the python version. Change-Id: Ida3d6c9bb46f6d826f45538e4ceaa4fc1e771ff5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2115 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: build bot (Jenkins)
2013-01-05ARMv7: drop __ASSEMBLY__Stefan Reinauer
We moved to using __ASSEMBLER__ years ago since it is set by as. Change-Id: I60103ba23ebe87be1d0bc63beed0ef5b05eed4f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2111 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-05Update 3rdparty mark to latest repositoryStefan Reinauer
Change-Id: I59fca4427345c7e677138b944613a1554d5a8331 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2110 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-05ARMv7: drop __KERNEL__Stefan Reinauer
It's a bad Linux heritage.. We have no userland in firmware. Change-Id: Ib19e5ba713078ca37514571213d19f418417b964 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2108 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04cbfstool: Fix warnings on OS XStefan Reinauer
Most hton and noth functions are already available through the system headers we include on OS X, causing the compiler to warn about duplicate definitions. Change-Id: Id81852dfc028cf0c48155048c54d431436889c0e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2106 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-01-04Flatten the treeRonald G. Minnich
It makes no sense to have directories with one file. Change-Id: I65ba93dda5e6a4bcc5a7cc049c1378ebf5d6abcd Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2105 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04Revert "armv7: pass bootblock offset from Kconfig into cbfstool"Ronald G. Minnich
This reverts commit ec8d35fe911ab35a5f40fd5b452f5463857b244a We are almost certain that this is not necessary. Change-Id: I70e94f883be95655da00a0b127ed9ffd7c81c63b Reviewed-on: http://review.coreboot.org/2104 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-01-04ARMv7: Make ABI compatible to reference toolchainStefan Reinauer
Our reference toolchain uses -mabi=aapcs whereas we started forcing -mabi=aapcs-linux. Drop this to prevent ABI incompatibility. Also drop -fno-common since that's set in the top level Makefile.inc already. Change-Id: I4afdcf5da9a5d86c2f9e5de5c7d523ccd2f5f1e0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2103 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04ARMv7: drop libgcc copyStefan Reinauer
We accidently checked in some files from libgcc as well as a Makefile from u-boot and a duplicate implementation of div0. Drop all those files to reduce the confusion. Change-Id: I8ff6eabbced6f663813f8cc55f19c81839d03477 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2102 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Clean up ARMv7 architecture KconfigStefan Reinauer
There was a misuse of bool that would cause the dcache policy to not be set up correctly, but instead present options "y" and "n" in the Kconfig menu. Also, TINY_BOOTBLOCK was removed a while ago, everything is TINY_BOOTBLOCK now. Hence remove the option. Change-Id: I5c28ac828955c69614c7bdaf106f79db51e68723 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2101 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Make PCIe config options depend on PCIe supportStefan Reinauer
Change-Id: I42452a044dc75e35876fcea1736481e538eed663 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2100 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04rd890: clear IO-APIC before setupAladyshev Konstantin
Add function "clear_ioapic" before "setup_ioapic" for RD890 northbridge like it is done for SB700 and SB800 chipsets ("amd/cimx/sb{7,8}00"). No functionality change is noticed. Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636 Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2045 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-04cbmem utility: Use mmap instead of fseek/freadStefan Reinauer
The kernel on Ubuntu 12.04LTS does not allow to use fseek/fread to read the coreboot table at the end of memory but will instead abort cbmem with a "Bad Address" error. Whether that is a security feature (some variation of CONFIG_STRICT_DEVMEM) or a kernel bug is not yet clear, however using mmap works nicely. Change-Id: I796b4cd2096fcdcc65c1361ba990cd467f13877e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2097 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-01-04Tyan s8226: change lapic of lapic_cluster 0 to 0x10Siyuan Wang
There are two CPUs on s8226 and each CPU has 8 cores. CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27. So the first core's lapic is 0x10 rather than 0x20. Change-Id: I925114d44f2f4974eb62c3832d8c9139a2a06c96 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/2099 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04Change "VERSION*" to more determined name "CBFS_HEADER_VERSION*".Hung-Te Lin
The 'VERSION' in CBFS header file is confusing and may conflict when being used in libpayload. Change-Id: I24cce0cd73540e38d96f222df0a65414b16f6260 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/2098 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-01-04cleanup some exynos5250 uart codeDavid Hendricks
This just cleans out some unused headers and tidies up the early serial code. TODO: Clean-up or replace FDT code, make "base_port" easier to configure. A bit of cleanup based on earlier patches. Change-Id: Ie77ee6d4935346e0053c09252055662f1a45d5f5 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2084 Tested-by: build bot (Jenkins)
2013-01-04enable early serial console on exynos5250David Hendricks
Change-Id: Ib16308c72b86860e80caec96202c42991a7b1d1a Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2085 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04make early serial console support more genericDavid Hendricks
This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. The UART code structure needs some rework, but the use of ROMCC, romstage, and then ramstage makes things complex. uart.h now includes all .h files for all uarts. All 2 of them. This is actually a simplifying change. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2086 Tested-by: build bot (Jenkins)
2013-01-04update CFLAGS for armv7David Hendricks
This updates $CFLAGS used for armv7. Most of them were just added to be consistent with what u-boot does. The important ones here are -march=armv7-a and -mthumb (to allow 16-bit Thumb instructions). I removed the hard float support because it got errors and coreboot should never use floats anyway. We're still having trouble with enums but I want to see how far it gets with this patch. Also, put the flags in a form that makes diffs easier to read. It's almost impossible otherwise. Finally, move some flags to the architecture Makefile, and rely on the fact that some are set for all architectures. Depends-On: I6f730d017391f9ec4401cdfd34931c869df10a9e Change-Id: Ia8a1ae22959933e06f7b996d1832cea40819f1ff Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2075 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03Rename mainboard_smi.c to smihandler.cPatrick Georgi
This mirrors the naming convention of handlers in northbridge and southbridge. Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2058 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03Add the push default to 'make gitconfig'Ronald G. Minnich
It's too easy to forget this and it's kind of important, so Just Add It. Change-Id: Ic7ab7658425a98d5d435bfef46f89cc6a56c7284 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2096 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-03armv7: pass bootblock offset from Kconfig into cbfstoolDavid Hendricks
This replaces a somewhat useless calculation used earlier (which always evaluated to 0) with an offset to specify the location of the Coreboot bootblock. Change-Id: Ib85aaccf138cebeb6bf8aedf82308861206dff48 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2094 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03snow: Stuff to support building image with BL1David Hendricks
This patch does two things which will take effect in follow-up patches: 1. Add an intermediate Makefile rule for dd'ing BL1 into the coreboot.rom pre-image. This is modeled after a similar hack for the bd82x6x southbridge. 2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to pass the bootblock offset into cbfstool. Change-Id: I89da255dc903c387b754b06a11bb3439035ead87 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2093 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-03add user-specified offset when creating armv7 cbfs imageDavid Hendricks
The "offs" provided on the command-line was not taken into account when creating an image for armv7... Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2092 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 17:07:44 +0000