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2016-07-17mainboard/amd: add support for F2950 system boardAndrey Korolyov
F2950 SBC, also known as TONK 1201/TONK 1202, was originally produced as a Centerm F2950 using DB800 reference design. Common configuration does include a 600 MHz GeodeLX CPU underclocked to 500 or 400 MHz, 128 or 512 MiB of RAM in the single SODIMM slot and 128 or 512 MB IDE DOM. The board does have three USB 2.0 ports (none of them possessing debug capabilities), PS/2, VGA, Geode audio in/out and the serial port. EEPROM needs to be soldered out and flashed externally at the time of this message because flashrom would neither be able to dump BIOS correctly while running vendor BIOS nor write flash contents. All peripherals were tested against Linux 3.16 and seem to work flawlessly. At the moment of this commit coreboot does not pass PCI_COMMAND_IO from the configuration space to SeaBIOS, thereby preventing VGA OPROM from being executed. This would be fixed in the SeaBIOS itself or in a subsequent commit. As a workaround, user may put VGA OPROM to vgaroms/seavgabios.bin in CBFS. Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4 Reviewed-on: https://review.coreboot.org/15565 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-17acpi: Change API called to write the name for ACPI_DP_TYPE_CHILDHarsha Priya
The API called to write the name of the child table in the dp entry (type ACPI_DP_TYPE_CHILD) was not including the quotes, e.g., it was DAAD and not "DAAD". Thus, the kernel driver did not get the right information from SSDT. Change the API to acpigen_write_string() to fix the issue. Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8984e7 Reviewed-on: https://review.coreboot.org/15724 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-16buildgcc: Update the revision to 1.41Martin Roth
The binutils patch went in without updating the revision, so we need to update it now. This was done in commit bcfa7ccb (buildgcc: Update to binutils-2.26.1 & Fix aarch64 build issue) Change-Id: Ifad4a2e3973f1f60d0ea840945e2bd097e1b4474 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15712 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15intel/amenia: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Platform wakes up from S3 on lidopen. Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15618 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/apollolake: Properly disable PCIe root portsKane Chen
1. The hotplug feature needs to be disabled so that pcie root ports will be disabled by fsp 2. Correct PcieRootPortEn mapping. The correct mapping should be like below PcieRootPortEn[0] ==> 00:14.0 PcieRootPortEn[1] ==> 00:14.1 PcieRootPortEn[2] ==> 00:13.0 PcieRootPortEn[3] ==> 00:13.1 PcieRootPortEn[4] ==> 00:13.2 PcieRootPortEn[5] ==> 00:13.3 BUG=chrome-os-partner:54288 BRANCH=None TEST=Checked pcie root port is disabled properly and make sure pcie ports are coalesced. Also make sure the device will still be enabled after coalescence when pcie on function 0 is disabled devicetree Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/15595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15google/reef: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Reef board wakes up from S3 on lidopen. Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15intel/x4x: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15intel/pineview: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15715 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15AMD binaryPI: Use common romstage ram stackKyösti Mälkki
Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: I52d0bd7dac86822242400f68f6dc202f02d6e0f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AMD binaryPI: Split romstage ram stackKyösti Mälkki
Change-Id: Ibbff1fdb1af247550815532ef12f078229f12321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AMD binaryPI: Use common ACPI S3 recoveryKyösti Mälkki
Note that no binaryPI board has HAVE_ACPI_RESUME. Change-Id: Ic7d87aa81c75374dd1570cef412a3ca245285d58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15254 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AGESA: Use common romstage ram stackKyösti Mälkki
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15AGESA: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I8ce91088c5fa1a2d2abc53b23e423939fe759117 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15253 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15mainboards/skylake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15689 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15soc/intel/skylake: provide poweroff() implementationAaron Durbin
Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I9288dcee13347a8aa3f822ca3d75148ba2792859 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15688 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15mainboards/apollolake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15687 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15soc/intel/apollolake: provide poweroff() implementationAaron Durbin
Implement poweroff() by putting the chipset into ACPI S5 state. BUG=chrome-os-partner:54977 Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15686 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15ec/google/chromeec: provide common SMI handler helpersAaron Durbin
The mainboards which use the Chrome EC duplicate the same logic in the mainboard smi handler. Provide common helper functions for those boards to utilize. BUG=chrome-os-partner:54977 Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15685 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15lib: add poweroff() declarationAaron Durbin
Add a function to power off the system within the halt.h header. BUG=chrome-os-partner:54977 Change-Id: I21ca9de38d4ca67c77272031cc20f3f1d015f8fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15684 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15soc/intel/quark: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I034c083604892a5fa25dff3b50e327e0a885b021 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I884da90d24bc41e566a290f4135166d9e0cdf474 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15682 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/fsp_i89xx: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ibf2bc3ae89cb5a013cb1ccc439c906b00bf78d66 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ia113672fa3cb740cb193c23fd06181d9ce895ac3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/i82801gx: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I08fb52ca13a4355d95fe31516c43de18d40de140 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/i82801dx: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I29918fe70b5e511785ed920d8953de3281694be2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/ibexpeak: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I65270ddcb612f9c63d7dbb2409e4395f96e10a51 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15677 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/lynxpoint: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15676 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15southbridge/intel/bd82x6x: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ie709e5d232c474b41f2ea73d3785a7975d6604ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/fsp_baytrail: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I1ff1517ded2d43e3790d980599e756d0d064f75c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/broadwell: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I99d909ee72c3abebb1e9c8ebf44137465264bf0d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15672 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-07-15soc/intel/skylake: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15671 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15soc/intel/braswell: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15670 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15soc/intel/baytrail: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15669 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/common: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15668 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/apollolake: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15667 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-15arch/x86: provide common Intel ACPI hardware definitionsAaron Durbin
In the ACPI specification the PM1 register locations are well defined, but the sleep type values are hardware specific. That said, the Intel chipsets have been consistent with the values they use. Therefore, provide those hardware definitions as well a helper function for translating the hardware values to the more high level ACPI sleep values. BUG=chrome-os-partner:54977 Change-Id: Iaeda082e362de5d440256d05e6885b3388ffbe43 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-15drivers/intel/fsp1_1: align on using ACPI_Sx definitionsAaron Durbin
The SLEEP_STATE_x definitions in the chipsets utilizing FSP 1.1. driver have the exact same values as the ACPI_Sx definitions. The chipsets will be moved over subsequently, but updating this first allows the per-chipset patches to be isolated. BUG=chrome-os-partner:54977 Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15665 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15mainboards: remove direct acpi_slp_type usageAaron Durbin
Use the acpi_is_wakeup_s3() API instead of comparing a raw value to a global variable. This allows for easier refactoring. Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15690 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15arch/x86: provide common ACPI_Sx constantsAaron Durbin
Instead of open coding the literal values provide more semantic symbol to be used. This will allow for aligning chipset code with this as well to reduce duplication. BUG=chrome-os-partner:54977 Change-Id: I022bf1eb258f7244f2e5aa2fb72b7b82e1900a5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15663 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-15soc/intel/skylake: don't duplicate setting ACPI sleep stateAaron Durbin
The ramstage main() in lib/hardwaremain.c has the logic to set the ACPI sleep state based on romstage_handoff. Thus, there's no need to do it a second time. Change-Id: I75172083587c8d4457c1466edb88d400f7ef2dd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15662 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15soc/intel/braswell: don't duplicate setting ACPI sleep stateAaron Durbin
The ramstage main() in lib/hardwaremain.c has the logic to set the ACPI sleep state based on romstage_handoff. Thus, there's no need to do it a second time. Change-Id: I88af301024fd6f868f494a737d2cce14d85f8241 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15661 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-15arch/riscv: Move CBMEM into RAMJonathan Neuschäfer
CBMEM should be placed at the top of RAM, which can be found by parsing the configuration string. Configuration string parsing isn't yet implemented, so I'll hard-code the CBMEM location for now. Change-Id: If4092d094a856f6783887c062d6682dd13a73b8f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15284 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-15chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sectionsPaul Kocialkowski
This fills up the RO_FRID, RW_FWID_A and RW_FWID_B FMAP sections with the relevant version from KERNELVERSION, padded to the right size and gap-filled with zeros. Change-Id: I45c724555f8e41be02b92ef2990bf6710be805c2 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15rockchip/rk3399: extend romstage rangeLin Huang
rk3399 sdram size is 192K, and there still some unused space. We need more romstage space to include the sdram config, so extend the romstage range. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: Ib827345fe646e985773e6ce3e98ac3f64317fffb Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 626ab15bb4ebb004d5294b948bbdecc77a72a484 Original-Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/359092 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15660 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: set kevin rev3 pwm regulator initial value to 0.95vLin Huang
kevin rev3 pwm regulator ripple is still not great, especially for center logic. To make sdram at 800MHz stable, raise it to 0.95v. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If4a15eb7398eea8214cb58422bca7cfb5f4a051a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d29bc581effb0008eb196685aa22dd65b5d478a5 Original-Change-Id: Ideec9c3ab2f919af732719ed2f6a702068d99c8f Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/359130 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15659 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15Google Mainboards: Increase RO coreboot size on flashDaisuke Nojiri
Bitmap images will be moved to CBFS from GBB. This patch adjusts the flash map accordingly for rambi, samus, peppy, parrot, falco, panther, auron, and strago. BUG=chromium:622501 BRANCH=tot TEST=emerge-{samus,falco} chromeos-bootimage CQ-DEPEND=CL:354710,CL:355100 Change-Id: I6b59d0fd4cc7929f0de5317650faf17c269c4178 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 201a82311ba539b9b02d546ba331ff5bf73e0edf Original-Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355040 Reviewed-on: https://review.coreboot.org/15658 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15rockchip/rk3399: Remove empty function in sdram.cDerek Basehore
This removes an empty function for sdram training. If it's needed later, we can always add it back. BRANCH=none BUG=none TEST=build and boot firmware for kevin/gru Change-Id: Id526ef86cf5044894a1a736cc39f10d32f49c072 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3e93461b96bfadc08bf0b46cf99052d9cdffa422 Original-Change-Id: I6bf77d2f81719c68cd78722c3fe9ae547ea1e79c Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354164 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15657 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 08:28:00 +0000