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2019-10-18build: Mark bootblock files on x86 as IBBPatrick Rudolph
* Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-10-18util/cbfstool: Add optional argument ibbPhilipp Deppenwiese
* Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/intel/common: lpc/espi: fix wrong lock bitMichael Niewöhner
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-18superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.aslPavel Sayekat
This port is based on NCT6776 Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory supportFrans Hendriks
FBG-1701 revision 1.3 will use Kingston onboard memory. Add Kingston SPD file. When Samsung memory configuration is disabled use cpld_read_pcb_version() for using correct SPD data. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 revision 1.3 Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792 Reviewed-by: Wim Vervoorn Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18superio/smsc: Restore sio1036Marshall Dawson
Change d3a1a417 "src/superio: Remove unused superio chips" removed all unused devices except for ones used on mainboards still under review. The SMSC 1036 was inadvertenly also removed as well. This device is used in debug cards that may be connected to AMD CRBs. This patch restores the smsc1036 directory as-is and then corrects the following lint messages. * WARNING: Prefer 'unsigned int' to bare use of 'unsigned' * ERROR: else should follow close brace '}' * WARNING: braces {} are not necessary for single statement blocks Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/facebook/fbg1701: separate cpld supportWim Vervoorn
Move all code involving the cpld to a single file. Rename mainboard_read_pcb_version() to cpld_read_pcb_version(). BUG=N/A TEST=tested on fbg1701 board Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18mb/google/hatch/var/dratini: Update DPTF parametersWisley Chen
The change applies the DPTF parameters. BUG=b:142849037 TEST=build and verified by thermal team Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-18soc/mediatek/mt8183: Compress calibration blob with LZ4Hung-Te Lin
The DRAM calibration blob can be compressed using pre-RAM algorithm (currently LZ4), which will save ~12ms in boot time. On Kodama, boot time difference: Before: 1,082,711 After: 1,070,309 BUG=b:139099592,b:117953502 TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed) BRANCH=kukui Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-18mb/google: Shrink GBB section sizeHung-Te Lin
Chrome OS firmware images have moved bitmap resources from GBB into CBFS for a long time, so the GBB should only hold firmware keys and HWID, that is usually less than 10k. ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but many recent x86 simply copy from old settings and may run out of space when we want to add more resources, for example EC RO software sync. Note, changing the GBB section (inside RO) implies RO update, so this change *must not* be cherry-picked back to old firmware branches if some devices were already shipped. BRANCH=none BUG=None TEST=make # board=darllion,hatch,kahlee,octopus,sarien Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-18mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functionsWerner Zeh
The two GPIO functions variant_gpio_table() and variant_early_gpio_table() provide the pointer to the variants GPIO table for late and early GPIO init. As these functions are variant dependent the keyword __weak must not be used as otherwise the linker might choose the tables from the baseboard. This patch removes the __weak definition making these functions overriding the general ones in baseboard/gpio.c. Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36094 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/mediatek/mt8183: Pass impedance data as a function argumentYu-Ping Wu
To make data flow more explicit, global variable 'impedance' is replaced with a local variable, which is passed as a function argument. BUG=none BRANCH=kukui TEST=Krane boots correctly Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switchHuayang Duan
The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with multiple frequencies to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequencyHuayang Duan
This patch supports voltage adjustment for each DRAM frequency, which is neccesary to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-18soc/mediatek/mt8183: Allow modifying vddq voltageHsin-Hsiung Wang
DRAM DVFS needs to be calibrated with different vddq voltages to get correct parameters. A new API is added to allow changing vddq voltage. BUG=b:80501386 BRANCH=none TEST=measure vddq voltage with multimeter Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35147 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/mediatek/mt8183: Allow modifying vdram1 voltageHsin-Hsiung Wang
DRAM DVFS needs to be calibrated with different vdram1 voltages to get correct parameters. A new API is added to allow changing vdram1 voltage. BUG=b:80501386 BRANCH=none TEST=measure vdram1 voltage with multimeter Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33186 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-18soc/mediatek/mt8183: Share console for calibration blob outputHung-Te Lin
Most coreboot debug messages are sent to UART and cbmem console, and we also want to collect DRAM calibration module output, especially for cbmem console (so we can see the logs after kernel is up). Instead of sharing whole cbmem/cbtable/cbmemconsole implementations, we want to simplify that by a simple function pointer so output can be preserved by do_putchar, which internally sends data to all registered consoles (usually cbmem console and UART). BUG=b:139099592 TEST=make; boots properly for full-k, with and without serial console. BRANCH=kukui Change-Id: I1cf16711caf3831e99e17b522b86694524425116 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36056 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17util/abuild: Have abuild generate the .xcompile if it doesn't existRaul E Rangel
Previously if .xcompile was missing, abuild would silently ignore the error. With https://review.coreboot.org/c/coreboot/+/34241 we now check the return code so abuild started failing. We should generate the .xcompile if it doesn't exist. The Makefile will handle that so we include it as the first Makefile. We then need to override the default target so we don't use the one from the Makefile. BUG=b:112267918 TEST=ran abuild and made sure it generated a .xcompile in the root. Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-17MAINTAINERS: Add supermicro/x11-lga1151-seriesMichael Niewöhner
Add an entry for mb/supermicro/x11-lga1151-series and add myself to the list of maintainers. Change-Id: I634d251b4323c4f05edd553a9fa82e0f8c53773b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-17cpu/amd/{agesa,pi}: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans
AGESA and binaryPI set the whole CACHE_ROM_SIZE to WRPROT during the romstage and do not reference the CONFIG_XIP_ROM_SIZE symbol. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-17mb/lenovo/x201: Add VBOOT supportArthur Heymans
Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between RW_A and recovery, which works quite well as a developer mode to test RW_A with the COREBOOT slot as a fallback. Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-17nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startupArthur Heymans
During the raminit the CPU gets reset but the platform does not. To deal with TPM init failure (a TPM can only be started up once) ignore the invalid POSTINIT return code. Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36055 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17security/tpm: Add a Kconfig to disregard INVALID_POSTINIT on startupArthur Heymans
There are use cases where TPM has already been set up in a previous stage, e.g. TXT or when a CPU reset without a platform reset happens. If this is the case the TPM startup will return a INVALID_POSTINIT (return code 0x26). This adds a Kconfig to allow platforms to disregard that return code. Change-Id: I238b30866f78608c414de877b05a73cf8fdb9bbd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-17soc/mediatek/mt8183: Verify checksum of cached calibration dataYu-Ping Wu
The checksum is stored in the header of calibration data and saved to SPI flash. After reading the data from flash, checksum is used to verify the integrity of the calibration parameters. BUG=b:139099592 BRANCH=kukui TEST=Calibration data successfully loaded from flash Change-Id: Ie4a0688ed6e560d4c0c6b316f44e52fd10d71a9d Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Remove unnecessary DRAM register settingsYu-Ping Wu
In broadcast mode we only need to set registers for channel 0 instead of all channels. BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Fix DDR phy config numberYu-Ping Wu
Some typos are fixed to make DVFS switch work. BUG=b:142358843 BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Refactor DRAM init by bit fields APIHung-Te Lin
Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and other bit field helpers. Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17soc/mediatek/mt8183: Improve code formattingYu-Ping Wu
This patch contains some minor changes including: - Use lowercase hex literals - Combine short lines - Remove unnecessary curly braces - Simplify struct initialization - Leverage macro _SELPH_DQS_BITS - Ensure whitespaces around binary operators - Remove extra whitespaces after commas - Change log level and remove unnecessary debug logs BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-10-17soc/mediatek/mt8183: Handle memory test failureYu-Ping Wu
If DRAM calibration fails or mem test fails using the cached calibration results stored in flash, rerun DRAM full calibration. If partial calibration fails or the mem test following it fails, hang forever. Partial calibration acts as a fallback approach in case of full calibration failure. Therefore, if it fails, there would be no other ways to initialize DRAM. Instead of falling into reboot loop and draining out of battery, it is better to just hang so that the end user may notice that and send to RMA. BUG=b:80501386,b:139099592 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35481 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-17nb/intel/nehalem: Only enable_smbus onceArthur Heymans
This is already done in nb/intel/nehalem/romstage.c. Change-Id: I2dc34af874ac96af31ca9ebe6a43b2805da32d18 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-17nb/intel/nehalem: use pmclib to detect S3 resumeArthur Heymans
During the raminit the CPU gets reset, so reprogram those bits in PM1_CNT such that the CPU remains aware that this is a S3 resume path after the reset. Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-17nb/intel/nehalem: Add some debug outputArthur Heymans
Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-17nb/intel/nehalem: Change the output verbosity of raminit timingsArthur Heymans
This decreases the output verbosity of RAM_DEBUG to be useful. Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-16mb/google/hatch/akemi: Tune I2C bus 1 clockPeichao Wang
Tune I2C bus 1 clock and insure it meets I2C spec. BUG=b:142683257 TEST==flash coreboot to the DUT and measure I2C bus 1 clock frequency less than 400KHz Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-10-16mb/google/hatch/var/dratini: Add enable pin for elan touchscreenWisley Chen
Add enable pin for elan touchscreen BUG=b:142710871 TEST=touchscreen work Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-10-16mb/google/hatch/var/dratini: update goodix power sequenceWisley Chen
Update power sequence to meet spec. BUG=b:142710867 TEST=touchscreen work, and make sure power sequence to meet spec with vendor. Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36060 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-16mb/google/drallion: Add new SPD file for drallionBora Guvendik
Add the SPD data for MT40A1G16KD-062E:E BUG=b:139397313 TEST=Compile successfully. Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-10-16mb/google/octopus: Override VBT selection for BlooguardTony Huang
Disable DRRS on Blooguard SKU - 49, 50, 51, 52 BUG=b:142632381 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is blooguard. Cq-Depend: chrome-internal:1983227 Change-Id: I36a313fd2beacb878da7383f733e206067c1c0fb Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-10-16soc/sifive/fu540: test and fix code of fu540 spiXiang Wang
I tested the SPI through the SD card and fixed sd card communication problem. Added two functions (claim_bus and release_bus). Setting CS signal is invalid by default. Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-16mainboard/ocp/monolake: Hide IIO root ports before memory initAndrey Petrov
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-16mb/facebook/fbg1701: correct clang issuesWim Vervoorn
Corrected clang issues in fbg1701 directory. BUG=N/A TEST=build Change-Id: I968bf8418aa457a7ebd28096bd92a64211bf86dd Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-16Documentation/mainboard/facebook: Add rev 1.3Wim Vervoorn
Add rev 1.3 of the fbg1701 board. This adds Kingston memory. BUG=none TEST=none Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16sb/intel/bd82x6x/lpc: Set up default LPC decode rangesArthur Heymans
This sets up some common default LPC decode ranges in a common place. This may set up more decode ranges than needed but that typically does not hurt. Mainboards needing additional ranges can do so in the mainboard pch_enable_lpc hook. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16intel/broadwell: Hook libgfxinit upNico Huber
As VGA_ROM_RUN and libgfxinit are mutually exclusive in Kconfig, we don't have to guard all the VGA BIOS if's and can assume gfx_get_init_done() returns 0 until all the quirks are handled. Then, we can run libgfxinit. Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/20100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-16intel/broadwell: Implement proper backlight PWM configNico Huber
Port the backlight-PWM handling from Skylake instead of the previously used Haswell version. We use a 200Hz PWM signal for all boards. Which is higher than the previous devicetree value, 183Hz, but that was over- ridden by the VBIOS anyway. 200Hz is still very low, considering LED backlights, but accurate values are unknown at this time. Lynx Point, the PCH for Haswell and Broadwell, is a transition point for the backlight-PWM config. On platforms with a PCH, we have: o Before Lynx Point: The CPU has no PWM pin and sends the PWM duty-cycle setting to the PCH. The PCH can choose to ignore that and use its own setting (BLM_PCH_OVERRIDE_ENABLE). We use the CPU setting on these platforms. o Lynx Point + Haswell: The CPU has an additional PWM pin but can be set up to send its setting to the PCH as before. The PCH can still choose to ignore that. We use the CPU setting with Haswell. o Lynx Point + Broadwell: The CPU can't send its setting to the PCH anymore. BLM_PCH_ OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is used (it virtually always is). We have to use the PCH setting in this case. o After Lynx Point: Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is implied and the bit not implemented anymore. Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-16mb/lenovo/x201: Fix Linux shutting down on s3 resumeArthur Heymans
On some configuration coreboot boots too fast and the EC reports the max temperature, resulting in Linux shutting down immediately. Change-Id: I610c7c9fbf2130566d3c2c758f1796314d3a0973 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-10-16src/superio: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/mb: Remove unused 'include <arch/io.h>'Elyes HAOUAS
Change-Id: I03461cb9e87b4ddd599e5601637a75b012694e7c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16src/superio: Remove unused 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16postcar: Fix linking error with disabled postcar consolePatrick Rudolph
Link files to provide snprintf used by VBOOT code. Change-Id: I040c3952c22893da5aae11b20a618aa4006c6c58 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 18:30:20 +0000