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2019-01-11Revert "cpu/amd: Use `get_option()`"Paul Menzel
This reverts commit 6fffd70435084fb1d3237fcb1a11f11849721e8f. Doing more tests on the Asus KGPE-D16, it seems to cause a reboot loop quite often. Therefore, revert the commit. The problem might be caused by the spinlocks used by `get_option()`, and which are not used by `read_option()`. Change-Id: Ic25129aa71c8e8e40a65bb2658de78005766fea8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11console/Kconfig: Fix dependency of FIXED_UART_FOR_CONSOLENico Huber
The Kconfig declaration for FIXED_UART_FOR_CONSOLE was accidentally placed inside an `if CONSOLE_SERIAL` in a96e66a (soc/intel: Clean mess around UART_DEBUG). TEST=Start a clean config, select intel/leafhill and disable serial console. Confirm that config can be saved without error. Change-Id: Ie41687e91af11a13697cbe25938dada2c74b40fb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11arch/x86/ebda: Don't trash the EBDA on the resume pathArthur Heymans
Clearing the EBDA was introduced with b4aaaa "Prepare the BIOS data areas before device init." which states that the purpose of setting up these area's is just to make sure they are sane. On the S3 path doing this is not needed and can even thrash data set up by payloads (mostly SeaBIOS) that used that memory. Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11cpu/intel/microcode: Support update before CAR entryArthur Heymans
Change-Id: Ie3c2d2e1bc79dcaffd9901e17f83ceeaabd1d659 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11arch/x86/lapic: Remove second stack poisoningKyösti Mälkki
It was already done once in c_start.S. Change-Id: I1cb0ea25251644dbd1127d177247a02ba52bb550 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-10mainboard/google/octopus: configure EC_AP_INT_ODLJett Rink
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards that support it. Also removing unnecessary IO standby support since we don't use this pin to wake up the SoC. BRANCH=octopus BUG=b:122552125,b:120679547 TEST=CTS tests with changes Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30788 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/fsp_broadwell_de: Drop MICROCODE_BLOB_NOT_HOOKED_UPNico Huber
It's been hooked up in the meantime. Change-Id: I64176b09e375034189000ea4308c58771f0019a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30812 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10northbridge/amdfam10: Deal with PCI_ADDR() betterKyösti Mälkki
PCI_ADDR() is tightly coupled with different setup_resource_map() variants so move the declaration away from global namespace. In the implementation of setup_resource_map() use the bottom 12 bits as the register mask like the other variants do already. Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30784 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10amdfam10 boards: Simplify early resourcemapKyösti Mälkki
Purpose of the table is to load initial address maps on PCI function 0:18.1. Provide a macro of its own so it is clear no other PCI devfn is accessed here. Change-Id: Ic146207580a5625c4f6799693157b02422bef00a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10sb/nvidia/mcp55: Avoid confusion with PCI_ADDR()Kyösti Mälkki
What you see in the table are not the PCI devices that will be written to. Use a helper MCP55_DEV() to make you look twice what is actually done. Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10sb/nvidia/ck804: Avoid confusion with PCI_ADDR()Kyösti Mälkki
What you see in the table are not the PCI devices that will be written to. Use a helper CK804_DEV() to make you look twice what is actually done. Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10amdfam10 boards: Drop extern on apicid_sp5100Kyösti Mälkki
The value get_bus_conf() initialises this value to is discarded. Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TOPatrick Georgi
TCO2_STS_SECOND_TO was renamed to TCO_STS_SECOND_TO but one use slipped through. Change-Id: I9e3b1cc5cb2f319db35416edf6cea612d755d40a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30805 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10crossgcc: Update acpica to version 20190108Elyes HAOUAS
changes in this version: https://acpica.org/node/164 Change-Id: Iff7fb6990f69f658c41ec115a3383ec902d8300f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-10device/pci_device: Do not break tree topologyKyösti Mälkki
Fix regression introduced with commit ad7674e device: Introduce pcidev_on_root() and friends Function pci_scan_bus() breaks bus->children link in the devicetree topology while scanning a bus. While the scan is in progress, accessing PCI devices with number higher than what is being probed was not possible because new pcidev_on_root() relies on having proper topology present at any time. Change-Id: I7bb497f7390628dd2f0310b380f199783a888c4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-10sb/intel/common: Show "Add EC firmware" only for boards that need itJan Tatje
Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to enable this option for boards that need it. The following list of boards requiring this was provided by Lijian Zhao: 1. intel/cannonlake_rvp 2. intel/coffeelake_rvp 3. intel/icelake_rvp 4. google/sarien 5. google/hatch Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10google/kukui: Correct boardid sources and add sku_idHung-Te Lin
Kukui is going to use ADC#4 as SKU ID, and utilizing EC BoardID as global board_id (i.e., board revision). BUG=b:122060615 TEST=make; manually tested on Kukui P1 board. Change-Id: I7bba368c141a7ba6db11f24b8e8e7158f0fc729e Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/30617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10google/kukui: Complete board ID ADC valuesHung-Te Lin
The ID from ADC on Kukui supports 16 different values and we should list all voltage values ahead. BUG=b:80501386 TEST=make; manually verified on Kukui P1 Change-Id: Ic3abe07abfe818ca68e180c262fd431d1167b801 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/30619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10google/kukui: Correct boardid init valuesHung-Te Lin
From `boardid.h`, the uninitialized ID values should be BOARD_ID_INIT instead of BOARD_ID_UNKNOWN. BUG=b:80501386 TEST=make; manually verified on Kukui P1 Change-Id: Ie5267e575e38b92ec64a7317defbd00ee153fa0a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/30618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10mb/foxconn/g41s-k: Add g41m variantArthur Heymans
Was tested with the following: - 2 DIMM slots - USB - Ethernet NIC - automatic fan control - Libgfxinit with VGA, DVI (HDMI slot unpopulated) - PS2 Keyboard - SATA - PEG - S3 resume What does not work: - Using the second DIMM slot on a channel G41 can only handle 2 ranks per channel and on this mainboard 1 rank per DIMM slot. Supporting this would require too much raminit rework and is not worth it (at least for me) Change-Id: I67784038ef929f561b82365f00db70a69c024321 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAPDuncan Laurie
1) Add a Platform Data Region called SI_PDR which is allocated in the flash descriptor for this platform 2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile storage. 3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG so it is clear they are associated. 4) Move the RW_DIAG region to the start of the RW region so that once we can re-enable a larger BIOS region this sub-region will be in the uncached area since it is not accessed on a normal boot. BUG=b:119435206 TEST=tested on Arcada board to ensure expected regions are present Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10drivers/intel/fsp1_1: Add stack guardsArthur Heymans
This allows to check if stack overflows the car globals. Change-Id: I369b2d846f35914facb3e69cc762f7e555271bec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-10driver/spi/eon.c: Add the rest of >=1MB EON EN25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards, e.g. EN25QH32 chip entry for AMD Lenovo G505S laptop. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I8343a1741be5ea294de0773962c021428815934c Reviewed-on: https://review.coreboot.org/c/30744 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/fsp_broadwell_de/vtd: Silence warningPatrick Rudolph
Silence PCI resource warning due to missing set_resources. Change-Id: I8253e9ca137bda1cdd1c06273679693c4b7803ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-10arch/x86: Remove weak tsc_freq_mhz() implementationKyösti Mälkki
Build with TSC_CONSTANT_RATE must fail when this function is not implemented for the platform. Weak implementation causes division by zero in timer_monotonic_get() and turns udelay() into no delay. Change-Id: Id3b105ea3aac37cd0cba18ce2fb06d87a055486f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-10soc/intel/denverton_ns: Fix missing tsc_freq_mhz()Kyösti Mälkki
It was relying on bad weak implementation for postcar and verstage. Change-Id: I5a520e0166198c0565349c164f143f4a43649861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
2019-01-10mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-103rdparty/blobs: Update for current Intel microcodeNico Huber
The microcode included for `model_6xx` was for a 660, that path has changed. Change-Id: I09a41a8269cfdf8953bac10c9630922192851e73 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-10Untangle CBFS microcode updatesNico Huber
The option to specify a binary file name was added later for platforms that do not provide microcode updates in our blobs repository. Alas, it wasn't visible what platforms these are. And if you specified a file for a platform that already had one, they were all included together. Make it visible which platforms don't provide binaries with the new con- figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to include binaries by default or explicitly show that no files are inclu- ded (default to CPU_MICROCODE_CBFS_NONE). Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS. And clean up the visibility of options: Don't show CBFS related options on platforms that don't support it and don't show external file options if the platform uses special rules for multiple files (CPU_MICROCODE_ MULTIPLE_FILES). Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29934 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10mb/google/hatch: enable CPU cluster deviceAamir Bohra
Change-Id: I28c67fbdf2b4f371c4b533b64cad2c4376ca2bd2 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30785 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10aopen/dxplplusu: Move timestamps to common codeKyösti Mälkki
First initialisation is already in cpu/intel/car/romstage.c. Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10mb: Move timestamp_add_now to northbridge/amd/amdfam10Elyes HAOUAS
Also remove some commented code. Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN()Elyes HAOUAS
Change-Id: I731fd4ecfab679cd3d830a89bc82c56cf9008bc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10binaryPI: Drop warning on EXT_CONF_SUPPORTKyösti Mälkki
Copy-paste from fam15 code. Change-Id: Ic52031c57a8b659bff5ca03a66ec2291140d2233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-10mainboard/amd: Drop incorrect Kconfig selectKyösti Mälkki
Copy-paste from fam15. Change-Id: I87af312870063aaa498bbfc2f059f69dcdab0094 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-10southbridge/amd/cimx: Drop unused functionsKyösti Mälkki
Leftovers from attempts of using these with native (non-AGESA) amdfam10/15 support code. Change-Id: I8eaed338438e1de5baee462376e339e1439f72f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09soc/intel: Clean mess around UART_DEBUGNico Huber
Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation, we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09Veyron: fix sdram config for Hynix H9CCNNNBKTMLBR-NTDLoop_Wu
Sdram config sdram-lpddr3-hynix-4GB.inc for H9CCNNNBKTMLBR-NTD can't boot on Mickey. It's confirmed that the right config for Hynix H9CCNNNBKTMLBR-NTD is sdram-lpddr3-hynix-2GB-BK.inc. BUG=b:122239609 BRANCH=master TEST=boot on mickey Change-Id: Ifeaadda50d939e0c118cb7fe3964dcd08b709c2a Signed-off-by: Loop_Wu <Loop_Wu@asus.com> Reviewed-on: https://review.coreboot.org/c/30761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-09amdfam10 boards: Use smp_write_pci_intsrc()Kyösti Mälkki
Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I6c924a70d00a9139719f8078bbf1e4d04b576324 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09mainboard/h8scm_fam10: Use apicid_sr5650Kyösti Mälkki
Do this for consistency and to ease further bulk-sed work on those lines. Change-Id: Ic9706de4278d163d1ba0c0706ec5d4c6c87ffa45 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09amdfam10 boards: Use PCI_DEVFN()Kyösti Mälkki
Change-Id: I7b9aeaaa1cfa20efc9d187d91ece4eb9ee659c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09southbridge/nvidia/ck804: Drop leftover codeKyösti Mälkki
Code was for romcc romstage. Change-Id: If368610651ce950169ef71d9ed768a509c2a5c5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09mb/intel/kblrvp: Add helper function to get Board IdPraveen hodagatta pranesh
Add 2 helper function get_board_id() & get_spd_index() to read board id & spd index from EC. Rename the old get_board_id() function to get_ec_boardinfo(). BUG=None TEST= Tested on KBL RVP11, able to read the Board id (0x44) and verified in serial logs. not verified on KBL RVP8. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: Ie20bf0d45a3568c2c433e5b844bea86aac07c47d Reviewed-on: https://review.coreboot.org/c/30306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-09mb/intel/kblrvp: Enable overridetree support for variantsPraveen hodagatta pranesh
This patch add devicetree.cb in baseboard and overridetree.cb for RVP3, RVP7 and RVP8 variants. BUG= None TEST= build with BUILD_TIMELESS=1, static.c remains same on before & after enabling overridetree. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: Ib7d492e2a92aed10ad0426d57640d0ed56733847 Reviewed-on: https://review.coreboot.org/c/30623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09MAINTAINERS: Tag denverton-ns as Odd FixesNico Huber
And remove some maintainers that aren't even registered to Gerrit. Change-Id: I3a753b60eab6d7939c37181760bcfb4bc6e75f65 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29472 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-09agesawrapper.c: check if HOP_COUNT_TABLE exists before AmdInitLate()Krystian Hebel
If HOP_COUNT_TABLE doesn't exist AmdInitLate() returns error when creating CDIT, which scaries users. This patch turns off CDIT generation. After this patch AGESA_UNSUPPORTED is returned due to a bug in AGESA which cannot be walked around without disabling DMI table generation (`AGESA_STATUS Status = TRUE`, present in open source version of AGESA too). Change-Id: I868aa840ad3495a66a9d70b7803af237e7d5f049 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30475 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-09cpu/amd: Use `get_option()`Paul Menzel
Fix warnings on the console. coreboot-4.9-214-g0dd2014390 Mon Jan 7 15:17:13 UTC 2019 romstage starting... NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. Change-Id: I8501ff256676cd0ec4b59b28f4f1e0f2a9f74cac Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09Doc/mb/asrock/h81m-hds: Link to the Haswell documentationTristan Corrick
Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 17:48:11 +0000