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2015-04-05acpi: protect acpi generators from PRE_RAM & SMMAlexander Couzens
acpi generators run only in RAM stage. Change-Id: Ia2ab677848fef38976c85dda1c2773ae065856b0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9249 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-04-05mainboard/lenovo/x201: correct sata_port_mapAlexander Couzens
x201 has 2 sata ports. 1 port for hard drive and 1 port for the dock. Tested on x201 with hdd in port 1 + cdrom in port 2. Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8657 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-04-05intel/nehalem: rename copypasted smi finalizer functionAlexander Couzens
The nehalem smi finalize handler was just copied from sandybridge, without even changing the function name. TEST=Built and tested on x201t with additional patch to use finalizers Change-Id: Ifb44eeaaa6e03556deeb5d12ed1147e02d6d6eb9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8292 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-04-04build system: rename __BOOT_BLOCK__ and __VER_STAGE__Patrick Georgi
Drop the inner underscore for consistency. Follows the commit stated below. Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06 Based-on-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172 Reviewed-on: http://review.coreboot.org/9290 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-04-04build system x86: deprecate bootblock_lds and ldscripts variablesPatrick Georgi
Instead of keeping this separate variable around, add linker scripts to the $(class)-y source lists and let the build system sort things out. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I4af687becf2971e009cb077debc902d2f0722cfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04build system: use full (in-tree) pathsPatrick Georgi
So far we assumed that all files in *-srcs are below src/ which wasn't really true actually and will be less true with future changes. Fix up crt0.S handling on x86, which is covered by default rules due to this change. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Icae563c2d545b1aea809406e73faf3b417796a1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9288 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04rk3288: set cpu frequency up to 1.8GHzhuang lin
before the rkclk_init(), we must set rk808 buck1 voltage up to 1300mv BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1300mv and check the cpu frequency up to 1.8GHz Original-Change-Id: I6a8c6e35bd7cc6017f2def72876a9170977f206e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222957 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> (cherry picked from commit 2e7e7c265691250d4a1b3ff94fe70b0a05f23e16) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iff89d959456dd4d36f4293435caf7b4f7bdaf6fd Reviewed-on: http://review.coreboot.org/9260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04rk3288: guarantee i2c low period more than 1.3ushuang lin
change i2c clock low period and high period proportion to 7:3 guarantee the low period more than 1.3us BUG=None TEST=Boot on veyron_pinky rev2,check the i2c clock frequency Original-Change-Id: I235e9e3ff54ab3b9cabad36bab58a8409f7005a0 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223002 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 57a5d90d394086483e0dcdd6279678658d07d842) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I6b0c9dfa540354f6463ed90c9f3f9503a4d5749e Reviewed-on: http://review.coreboot.org/9259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04t132: Enable SMMU translationsFurquan Shaikh
BUG=None BRANCH=None TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit is set to 1 Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222770 Original-Reviewed-by: Olof Johansson <olofj@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397 Reviewed-on: http://review.coreboot.org/9258 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: Store ODMDATA from BCT into PMC scratch for use by kernelTom Warren
In able to do earlyprintk spew on LP0 resume, the kernel needs to know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info, and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word from the BCT copy stored in IRAM by the BootROM. BUG=chrome-os-partner:32015 BRANCH=none TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell on Rush and confirmed value is what's in odmdata.cfg. Original-Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222402 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f6a21afdb81f7d2ae90119c563535b4c87c9ade) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9819ffdf0f7618f0dd8dc50f81b5b26d6f94bfbd Reviewed-on: http://review.coreboot.org/9257 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: remove framebuffer reservationAaron Durbin
There's no need to reserve the framebuffer within coreboot. If the payloads need a framebuffer they can allocate one themselves. BUG=chrome-os-partner:31355 BRANCH=None TEST=Built and booted on ryu. Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221726 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2 Reviewed-on: http://review.coreboot.org/9256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04veyron_pinky/rk3288: Use KHz, MHz and GHz constantsJulius Werner
Use the previously added frequency constants in patch titled 'stddef: Add KHz, MHz and GHz constants'. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac Reviewed-on: http://review.coreboot.org/9254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04stddef: Add KHz, MHz and GHz constantsAaron Durbin
This patch adds some simple constants to more easily write and do math with frequencies, analogous to the existing KiB, MiB and GiB constants for sizes. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I1e708b0aa53533c9ab999793ca2273c6dc68b5f6 Reviewed-on: http://review.coreboot.org/9253 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04samus: Disable USB Port 5Duncan Laurie
This device is not used in current builds and should be disabled to help EMI. BUG=chrome-os-partner:34117 BRANCH=samus TEST=build and boot on samus Change-Id: I5c34f1f6c84d9de04a42e16fa32f57d4f9d1e478 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 00a9b2ad8512f84beff7358dad0ec028478c57d2 Original-Change-Id: I62541e343dcaa3cd31c81b73d8c27a5efcf3ad60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234403 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9282 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Enable turbo ratio if availableDuncan Laurie
When turning up the CPU frequency set it to turbo if that is a possibility. Also only set the frequency on the boot CPU since that is all we need it on, this will allow the 1-core turbo ratio. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I573eb7a507305814ec48cc2f624b8e6ddad43f84 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d408c1b462983c682d61c6c447692391c2b52183 Original-Change-Id: Ib5ad746767ee0a56bc7e59de679a9342f053c0e5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234401 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Broadwell: Pass TSC value to romstage_mainLee Leahy
The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9280 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Add table driven way to add platform specific reg_script routinesLee Leahy
Extend lib/reg_script.c to use a platform table to declare additional platform specific register access routine functions. REG_SCRIPT_TYPE_PLATFORM_BASE is the starting value for platform specific register types. Additional register access types may be defined above this value. The type and access routines are placed into reg_script_type_table. The Baytrail type value for IOSF was left the enumeration since it was already defined and is being used for Braswell. BRANCH=none BUG=None TEST=Use the following steps to test: 1. Build for a Baytrail platform 2. Build for the Samus platform 3. Add a platform_bus_table routine to a platform which returns the address of an array of reg_script_bus_entry structures and the number of entries in the array. Change-Id: Ic99d345c4b067c52b4e9c47e59ed4472a05bc1a5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2d9fecf4287dff6311a81d818603212248f1a248 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215645 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Change-Id: I7cd37abc5a08cadb3166d4048f65b919b86ab5db Original-Reviewed-on: https://chromium-review.googlesource.com/229612 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9279 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add new memory typeDuncan Laurie
Add a new memory type for the next build, and rename the existing ones to drop the Gb suffix. BUG=chrome-os-partner:33924 BRANCH=samus TEST=build and boot on samus Change-Id: Iedcd3823aa80c93fc2aadbc486d74b40c9bd4279 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bcc9827965182a7d0d5325189d55eb76f5c2f0e7 Original-Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230769 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9278 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Set codec PDM clock output to 3MHzBen Zhang
Currently the rt5677 codec outputs 6MHz PDM clock which is out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS pin is pulled down to PGND with a 47k resistor, so the expected PDM clock is 64*FS (~3MHz) according to its datasheet. The corresponding kernel patch that adds the PDM clock config option is https://chromium-review.googlesource.com/#/c/230303/ BUG=chrome-os-partner:33303 BRANCH=samus TEST=flash coreboot with this patch and see PDM CLK went from 6MHz to 3MHz on samus with a scope. Change-Id: Icf2c61930175bede1ee8ebc2b0fb17c2938b806c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9ba4597515b2fbcc72fa22e296357c454175648 Original-Change-Id: I09acdf47bab4f641981491a84197de234918435e Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230344 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: fix typo in pei_dataDuncan Laurie
This was copied and pasted more than it should have been... BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5008f2992d8ab3b952042415af6d7844788e14fc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bff4570dffa413c4fc4dfd8c49920f6b951e944a Original-Change-Id: I2af9a30f3df733af147e8759f78a9802d2296c0f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Add USB3 PHY tuning fields to PEI DATADuncan Laurie
These are board specific adjustments that can be made for each USB3 port. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change touchscreen bootloader mode i2c addressDuncan Laurie
This value apparently changed to 0x27 in the hardware but was never adjusted in firmware. BUG=chrome-os-partner:33790 BRANCH=samus TEST=build and boot on samus Change-Id: Ib610fc6522715e3c841c337d420ec63563bec798 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e01d3b47bf49861e9d53fc8db41890fe4c91ff9b Original-Change-Id: I10ca7b77068491e143f8bf2463b481eada910618 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9274 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GSPI0 interfaceDuncan Laurie
This will be connected to the coded for firmware upload. BUG=chrome-os-partner:33495 BRANCH=samus TEST=build and boot on samus, check that GSPI driver is loaded Change-Id: Ife41394e31af9dab03495b34609cb119525f9b19 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bbf26154da675845251c54f71d1df9df8d2a4fd5 Original-Change-Id: I25c91145aef8ca2aef229ffb27e8a45df659982e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228835 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9273 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen
BRANCH=master BUG=chrome-os-partner:33113 TEST=Build a image and test on Rambi. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I37add87e6fd3e7ad4eee09b8e0b312a2a89c7948 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 59b4c94be46b4397de7cb32726da9fa216e75a4c Original-Change-Id: I22c8f9730cc0e1ecc991f2dd7f2a1e7c548a1789 Original-Reviewed-on: https://chromium-review.googlesource.com/226654 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable GPIO9 as touchpad wakeDuncan Laurie
With EVT2 systems GPIO9 is now used for touchpad wake. BUG=chrome-os-partner:32232 BRANCH=samus TEST=suspend/resume by touchpad on samus, with kernel workaround to disable setting of T19 in atmel driver mxt_suspend() 51 | 2014-11-03 12:41:34 | ACPI Enter | S3 52 | 2014-11-03 12:41:37 | ACPI Wake | S3 53 | 2014-11-03 12:41:37 | Wake Source | GPIO | 9 Change-Id: I67c1a6591dc287fc780889950e78c731a5a65d44 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8512a6e5266edaf77d300f47bd26c501f00361d7 Original-Change-Id: I8120747986e694b64d464826f87c9afa68af157a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227157 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Update thermal max for broadwellDuncan Laurie
Broadwell Tj_max is 105C, update accordingly. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus Change-Id: I001e17287ebbcbfdd909428e149a95878734dab9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fb1de7a9e1d84f592b785a1b495e4aaf434f23a2 Original-Change-Id: If6a3fd682f4ee9b8010982870a61b76e33010fd4 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9270 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Assign GPIO2 to HP_AMP_SHDN_LBen Zhang
BUG=chrome-os-partner:29649 BRANCH=samus TEST=Audio playback to headphone works Change-Id: I35efa3b97abbba50cbee4c25acfaeb155fc1238f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e2c0ede19c6b700c8d0bf01ff9d3a54984c5d784 Original-Change-Id: Ib51aace52026688dc8972047e5d934c80138ff80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221294 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9269 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Make codec interrupt active highBen Zhang
The codec interrupt needs to be active high because multiple interrupt sources share this line: 1) Headphone plug detect 2) Mic present 3) Hotword detect These interrupt sources are OR-ed together. BUG=chrome-os-partner:29649 BRANCH=samus TEST=Jack detection works on samus Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980 Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220588 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510 Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380 Original-TEST=Build a BIOS image and check the value is applied correctly. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43 Original-Reviewed-on: https://chromium-review.googlesource.com/220475 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3 Reviewed-on: http://review.coreboot.org/9267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform data for jack detectBen Zhang
GPIO IRQ support has been added in upstream rt5677 driver, with new jack detect platform config options. BUG=chrome-os-partner:29649 BRANCH=samus TEST=headphone and mic detect works on Samus Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502 Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224513 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9266 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Change GPIO controller label to INT3437:00Duncan Laurie
This matches the label exported by the GPIO controller in the kernel and allows more speicific matches if there are other devices that also export GPIOs. BUG=chrome-os-partner:33098 BRANCH=samus TEST=crossystem wpsw_cur returns 1 Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14 Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224136 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Enable update screen for software syncDuncan Laurie
Since the PD software sync is slow enable support for displaying a screen telling the user that something is happening. BUG=chrome-os-partner:32379 BRANCH=samus TEST=manual testing: 1) in normal mode, with EC/PD in RW, ensure that they are rebooted to RO and the VGA Option ROM is loaded and the wait screen is displayed, and then the system is rebooted at the end and the VGA Option ROM is not loaded. 2) same as #1 with EC/PD in RO already, same result 3) same as #1 with system in developer mode, same result except there is no reboot at the end of software sync 4) same as #1 with system in developer mode and EC/PD in RO, ensure that there is no extra reboot at the beginning or end of software sync. Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2 Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223850 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add smbios_mainboard_version to define board versionDuncan Laurie
Instead of having this in mosys just have coreboot report the board version in SMBIOS tables. BUG=chrome-os-partner:32359 BRANCH=samus TEST=build and boot on samus, check /sys/class/dmi/id/product_version Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89 Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Fix building with USE=quiet-cbDuncan Laurie
This function needs to be available in different LOGLEVELs. BUG=chrome-os-partner:28234 BRANCH=samus TEST=USE=quiet-cb emerge-samus coreboot Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221540 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9262 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04samus: Add codec platform info in ACPIDuncan Laurie
This is the specific codec setup platform data for samus. BUG=chrome-os-partner:29649 BRANCH=samus TEST=emerge-samus coreboot Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221539 Original-Reviewed-by: Ben Zhang <benzh@chromium.org> Reviewed-on: http://review.coreboot.org/9261 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Drop (empty) google/snow mainboard directoryStefan Reinauer
Snow was renamed to daisy a long time ago. The only reason, it seems, the directory was still there, was a stray board_info.txt file that probably went in shortly after the rename. Change-Id: Iba08665e8486fcfeb214fcd05206a5f5683aea82 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9302 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04arm64: make secmon link with the manual templateAaron Durbin
Secmon needs a special build rule because of the objcopy -B operation required to include it in ramstage. Utilize the manual template so builds continue to work with upcoming build chnages. Note: secmon is actually missing symbols still so those still need to be addressed. That looks to be as if --gc-sections isn't be honored, but I'm actually thinking the symbols are just erroneously carried over as the references for these symbols don't show up in the symbol table: U coreboot_build U coreboot_extra_version U coreboot_version U default_baudrate U lb_add_console U lb_add_serial U uart_baudrate_divisor Change-Id: I41c75e93536b73c4304ef3a87dc39d448d1f00d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04armv4: Add verstage to armv4Furquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I7735a2148da5330f220bd9a87b09e9fe3e37ffd1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5e43dfe1aab813f45f1123b0e2432cdab5738d87) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If3d89ab79bae6d8f1b6f2d89b7693a79dca02476 Reviewed-on: http://review.coreboot.org/9252 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-04armv7: Add config option guard for verstage classFurquan Shaikh
Add files to verstage class depending upon value of CONFIG_ARCH_VERSTAGE_ARM_V7. BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I60fb8390abd9d378e38511d4f4ac323b43450232 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221321 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 4889cb73b0579155c083bb5fa2895b4d52ab0a56) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iea788ed72344343b2e7a3d91cd7f27ce20f4f177 Reviewed-on: http://review.coreboot.org/9251 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-04tegra124: use known-good drive for fast-train onlyNeil Chen
A higher drive setting is used for fast link training, once the link training succeeds, a known-good drive setting will be used for the main stream transactions. For full link training sequence, the sink devices may ask for a preferred drive setting, thus this drive setting should be used for the main stream transactions too. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219544 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6 Reviewed-on: http://review.coreboot.org/9248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04tegra124: add support for full DP link trainingNeil Chen
The original dp driver supports only fast link training and a special drive setting is used for the link training sequence. This might not be accepted by all panels. The better way is to go through full link training sequence to negotiate for a best drive setting. With the change, dp driver will try fast link training first, this is same as before. If it fails in fast link training, will try full link training. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219543 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 24966517d41252384af3c2784def36aebad42434) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c Reviewed-on: http://review.coreboot.org/9247 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-04rk3288: Replace SPI fifo_size with constantDavid Hendricks
rockchip_spi_slave has a fifo_size member which doesn't change. This just replaces the struct member with a #define. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9 Original-Reviewed-on: https://chromium-review.googlesource.com/220471 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit f76cce3b38ac37f4df8abf6eebb8f7c7b29da095) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3ab4eecfcce98aff3f6c9bd8f6c4e589784c60be Reviewed-on: http://review.coreboot.org/9246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04rk3288: Pass SPI bus speed in as parameter to init functionDavid Hendricks
This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c Reviewed-on: http://review.coreboot.org/9245 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04build system: Introduce manual file typePatrick Georgi
It's used for files with custom build rules, eg. the objcopy stuff surrounding smm and sipi_vector. Change-Id: Ie9ab4c9c6008ca42f82f768c5f33f90c7f5f4db5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9287 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04build system: Allow defining generic rulesPatrick Georgi
Provide a mechanism to define rules that apply for a given filetype (.c, .asl, ...) across all classes (ramstage, ...) Change-Id: If45c526d294e0374c32efef01f0213c6b78b1e43 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9286 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04build system: create proper dependency filesPatrick Georgi
Tell gcc what to use as target part of the generated rule. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: Ie4814143337abb3cf1e9e8db7e96201a517a17b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9285 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04x86: rename ldscript_failover.ld to failover.ldPatrick Georgi
The ldscript_ prefix is redundant. This is inspired by the commit listed below, but rewritten to match upstream, and split in smaller pieces to keep intent clear. Change-Id: I0f005c0c2abe2fdd6911a2c579cb7ec49ae5c0b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170 Reviewed-on: http://review.coreboot.org/9284 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-03tegra132: implement platform_prog_run()Aaron Durbin
The tegra132 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting romstage it runs ramstage from its faster armv8 core. Instead of hard coding the stage loading operations use run_ramstage(). Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8848 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03tegra124: implement platform_prog_run()Aaron Durbin
The tegra124 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting bootblock it runs romstage from its faster armv7 core. Instead of hard coding the stage loading operations use run_romstage(). Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8847 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03rmodule: use struct prog while loading rmodulesAaron Durbin
The rmod_stage_load structure contained the same fields as struct prog. In order to more closely integrate with the rest of program loading use struct prog. Change-Id: Ib7f45d0b3573e6d518864deacc4002802b11aa9c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9143 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 17:57:06 +0000