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2020-06-27sb/intel/i82801ix: Use pmutil.h definitionsAngel Pons
Also drop now-redundant definitions and include headers where needed. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801jx: Drop `p_cnt_throttling_supported`Angel Pons
The three mainboards using this southbridge do not support it. Change-Id: I006f1ec26c40f7e2dfc2ddedb017278455368bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42655 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801ix/fadt.c: Use pmutil.h definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ib4cdeaaaf75818fff21acb628d198781b07aec80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42654 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801jx/fadt.c: Use pmutil.h definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I572a9da0cba5d23c48c4cb06de4bb75f65f5b0b0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-06-27sb/intel/i82801gx/fadt.c: Align with i82801ixAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-27sb/intel/i82801gx/fadt.c: Reorder statementsAngel Pons
Change the order of the assignments to match that of i82801ix. This changes the binary but the effective result should be the same. Change-Id: Id720fce40e751295e629585d34017f10af2b5c7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42651 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/i82801gx: Move `acpi_fill_fadt` to fadt.cAngel Pons
At least i82801ix and i82801jx do this. Change-Id: I7ff2459d82eb7933ed80180a69f0f323b8ecd25f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-27sb/intel/i82801jx/fadt.c: Align with i82801ixAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I13b972440459a62777ee2a4688d1d8af147d8921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27sb/intel/i82801jx/fadt.c: Reorder statementsAngel Pons
Change the order of the assignments to match that of i82801ix. This changes the binary but the effective result should be the same. Change-Id: Ib190781f26f82f339eaf8039de459376ac0e3a5e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-27sb/intel/i82801jx: Move `acpi_fill_fadt` to fadt.cAngel Pons
At least i82801ix does this. Change-Id: Ic555ab17c2eca0399938d2842ca51628899c1544 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42637 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27mb/emulation/qemu-q35: Use common early SPI codeAngel Pons
Tested, it still boots. It is unknown whether this has any effect on emulated hardware, which is most likely not emulating SPI transfers. Change-Id: I44397c46dc0715697ca8680f418888804e4ea7e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27soc/intel/broadwell: Use common early SPI codeAngel Pons
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/lynxpoint: Use common early SPI codeAngel Pons
Change-Id: I6c6fbed077d2f169736aee77af3783c847cf3a06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/ibexpeak: Use common early SPI codeAngel Pons
Change-Id: Ib8cba1ae4fc269c925418965acf6956c1bfe0f79 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/i82801jx: Use common early SPI codeAngel Pons
Change-Id: If9efbde5939913b67852b377dd84cd4de1ec2718 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/i82801ix: Use common early SPI codeAngel Pons
Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/i82801gx: Use common early SPI codeAngel Pons
Change-Id: I44de4698d062508dd24f37b37014e09d95726c71 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-27sb/intel/bd82x6x: Use common early SPI codeAngel Pons
Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-27sb/intel/common: Add early SPI codeAngel Pons
All Intel southbridges with SPI perform this write. Put it inside a function in common code. Use a different name to avoid a name clash. As it is only one statement, make it inline so that it can be defined on the header itself. It is only called once per southbridge anyway. Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-26Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"Shelley Chen
This reverts commit 1408798637125f1707ded7215e22461c623a79a8. Reason for revert: Causing backlight issues in device. Will reland after more debugging to figure out the root cause. BUG=b:159370566 BRANCH=None TEST=boot up device and make sure when kernel is booted, backlight comes up. Change-Id: I643854c6c805d262539bbb482808e8c322059a49 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-06-26soc/rockchip: Use (Q) instead of @Stefan Reinauer
This way make V=1 will tell you what it's actually doing. Change-Id: I096bc2419e47a0b2a2454a792059464b27158cd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42818 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mb/mandolin/devicetree: clarify that Ethernet devices are internal MACsFelix Held
Change-Id: Ib7d696f4cc8f5fdcdf45e271b36664d085eb16d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mb/amd/mandolin/devicetree: disable unused internal ethernet controllersFelix Held
Change-Id: Id4c7ec02f37b35bbc36d40bb937b962cc6413d17 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42782 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26Fix up Docker paths to match jenkins nomenclatureStefan Reinauer
Jenkins is calling its build nodes "agent". Reflect that in the path names we use in configuration. Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mb/google/zork/Kconfig: remove unused option IRQ_SLOT_COUNTFelix Held
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which it doesn't. Change-Id: Ib5839a42f5133f5f84e1e1e4e587801b916ca571 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-26mb/amd/mandolin/devicetree: add comment about chip behind GPP bridge 3Felix Held
Change-Id: Ie1fcfb18a3ccf08c62210eec07d8965696f11da9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-26mainboard/prodrive/hermes: Enable EIST in DeviceTreeChristian Walter
Enable EIST option in the devicetree in order to make Windows aware of using Intel CPU Turbo Technology. Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-26mb/google/hatch: Set Reset Power Cycle Duration for hatch platformsSridhar Siricilla
Currently, Reset Power Cycle Duration is set with default value (4s). This adds around ~5 seconds of delay during power cycle or global reset. So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s to minimize the delay. Delay with Power Cycle or Global Reset: Existing behaviour: S0->S5 -> [ ~5 seconds delay ] -> S5->S0 With the patch: S0->S5 -> [ ~2 seconds delay ] -> S5->S0 Also, correct the comment mentioned for PchPmSlpAMinAssert. The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width to 98ms not 2s. Test=Verified on Hatch and Puff boards BUG=b:158634281 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/google/volteer: Enable HECI interfaceJamie Ryu
This is to enable Intel ME communication interface HECI1 by devicetree for PAVP with CSE Lite. BUG=b:159615125 TEST=Build and boot volteer. Run lspci and check pcie device 00:16.0 Communication controller: Intel Corporation Device a0e0 Change-Id: I68eb51c6a0af77982c060767993265764a2bc926 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-25mb/amd/mandolin: remove unused option IRQ_SLOT_COUNTFelix Held
That option is only relevant if the boards selects HAVE_PIRQ_TABLE which it doesn't. Change-Id: I76c098c7029ed9d797f6c4fb016eaa18854fadd3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25mb/amd/mandolin: add missing Kconfig type to CBFS_SIZE optionFelix Held
Change-Id: Ia4226537d17bb3732086980fb4e8de6bd1eaedbb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"Kyösti Mälkki
This reverts commit 4883252912665f56c8e7801fe03a26594a1e9d5d. Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as it does not have the same view of memory space. The prototypes xx_set/get_bar() are only valid for PSP as x86 cores will use the constant mapping defined in <amdblocks/acpimmio_map.h> The selected MMIO base address model depends of the architecture the stage is built for and, to current knowledge, nothing else. So the guards should have been with ENV_X86 vs ENV_ARM and not about CONFIG(VERSTAGE_BEFORE_BOOTBLOCK). For the ENV_ARM stage builds, <arch/io.h> file referenced in the previously added mmio_util_psp.c file has not been added to the tree. So there was some out-of-order submitting, which did not get caught as the build-testing of mixed-arch stages has not been incorporated into the tree yet. The previously added file mmio_util_psp.c is also 90% redundant with mmio_util.c. Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25Revert "mb/pcengines/apu2: Update GPIO Reads & writes"Kyösti Mälkki
This reverts commit 87f9fc8584c980dc4c73667f4c88d71d0e447a0c. GPIO configuration is supposed to be abstracted using <gpio.h> and the details of ACPMMIO GPIO bank hidden. This commit took it the opposite direction. Change-Id: Iacd80d1ca24c9d187ff2c8e68e57a609213bad08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42684 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25mb/amd/mandolin: Drop empty help textPatrick Georgi
kconfig complains. Change-Id: I281e4faa53cad5677864305feb9162b598ae483e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25util/abuild: Only update submodules oncePatrick Georgi
Without this, each build will try to update the submodules. Not necessarily a problem but git locks repos, creating spurious error messages. Change-Id: Iba20677d4b5f9365c92f7ed247ca56acb7d33b27 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-25mb/amd/mandolin: Quote string in Kconfig that contains /Patrick Georgi
Newer versions of Kconfig require that. Change-Id: I95f889d462ace1b912b5e6c7320973e8a826f3cb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25soc/intel/cannonlake: Add PchPmPwrCycDur to chip optionsSridhar Siricilla
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur from devicetree. The UPD determines the minimum time a platform will stay in reset during host partition reset with power cycle or global reset. This patch also ensures configured PchPmPwrCycDur value doesn't violate the PCH EDS specification. TEST=Verified on Hatch and Puff boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-25sb/intel/i82801ix/Kconfig: Sort options alphabeticallyAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I6f49af457f104dbf73e156f46ce09103ca9dccdb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42647 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25sb/intel/i82801jx/Kconfig: Sort options alphabeticallyAngel Pons
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: Ie5b87726cccf9fb8e45db39a6d6fba8ac4342f5f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25sb/intel/i82801{gx,jx}/nvs.h: Add include guardsAngel Pons
Change-Id: Ib7eb3469b03fd58afa1f6cb5822f7c6f1cac35e0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42645 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT`Angel Pons
Most other Intel southbridges call those `TPSV` and `TCRT` instead. Change-Id: Id4c30cd53abc544b743eb80696bfafe45929208e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42644 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
Not all FSPs based on FSP 2.1 supports the feature of external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE. Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is selected. Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake). Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-06-25soc/intel/xeon_sp: use edk2-stable202005 headersJonathan Zhang
Use edk2-stable202005 header files instead of UDK2017 header files, since FSP uses latest EDK2 code base. TESTED=Booted OCP Delta Lake server to OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3c845bceb201d4ffdf5adbf2af9aad6d6794a19d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42240 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25vendorcode/intel: Add edk2-stable202005 supportJonathan Zhang
This patch includes (edk2/edk2-stable202005) all required headers for edk2-stable202005 quarterly EDK2 tag from EDK2 github project using below command: >> git clone https://github.com/tianocore/edk2.git vedk2-stable202005 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3172505d9b829647ee1208c87623172f10b39310 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42239 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25vendorcode/google/chromeos: Add GOOG0016 _HID for Chrome OS ACPIDuncan Laurie
The Chrome OS ACPI code has always used a legacy PNP ID "GGL0001" for the ID. This is technically valid but we have an official ACPI ID now so I allocated "GOOG0016" for an ID and we can eventually retire the legacy PNP ID. This is being discussed on LKML as part of an effort to upstream the Chrome OS ACPI kernel driver: https://lkml.org/lkml/2020/4/13/315 Change-Id: I2e41fe419113b327618f8f98058ef7af657f2532 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-25arch/x86/smbios: Add more fields to be overriden for type 3 and 4Johnny Lin
For type 3, override chassis asset_tag_number with smbios_mainboard_asset_tag() and add two functions that can override chassis version and serial_number. For type 4 add smbios_processor_serial_number() to override serial_number. Tested on OCP Tioga Pass. Change-Id: I80c6244580a4428fab781d760071c51c7933abee Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-25drivers/ipmi: Add IPMI read FRU chassis info areaJohnny Lin
Implemented according to IPMI "Platform Management FRU Information Storage Definition" specification v1.0 for reading FRU data Chassis Info Area. Tested on OCP Tioga Pass. Change-Id: Ieb53c20f8eb4b7720bf1fe349e6aaebaa4c37247 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40306 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25drivers/ipmi: Add function read_data_string() to make code cleanerJohnny Lin
Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1da8abaa682af802e5cda65e5021069daf4ee717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-06-25mb/ocp/deltalake: Enable IPMI KCSMorgan Jang
Config the IO port for IPMI KCS and set bmc_boot_timeout for checking BMC self test result. TEST=Check if the BMC IPMI reponse data is correct or not. Change-Id: I675060299b486986ebc39d8f714615b3e13de89a Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41023 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBsJonathan Zhang
Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected). Such display is used for FSP debugging purpose. It adds small amount of boot time. Some UPD display log excerpts: UPD values for SiliconInit: 0x04: BifurcationPcie0 0x03: BifurcationPcie1 Some HOB display log excerpts: === FSP HOBs === 0x758df000: hob_list_ptr 0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF 0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-18 01:45:49 +0000