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2016-09-20gru: Add watchdog reset supportJulius Werner
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20vboot/vbnv_flash: Binary search to find last used entryRandall Spangler
This improves the previous linear search to O(log n). No change in storage format. BUG=chromium:640656 BRANCH=none TEST=Manual (test empty) flashrom -i RW_NVRAM -e Reboot; device should boot normally. (start using records) crossystem kern_nv=0xaab0 crossystem recovery_request=1 && reboot Device should go into recovery mode with reason 1 Reboot again; it should boot normally. crossystem kern_nv (should still contain 0xaab0) Repeat steps several times with request=2, 3, etc. flashrom -i RW_NVRAM -r nvdata Modify nvdata to copy the first record across all valid records flashrom -i RW_NVRAM -w nvdata Reboot; device should boot normally. Change-Id: Ieb97563ab92bd1d18a4f6a9e1d20157efe311fb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: db9bb2d3927ad57270d7acfd42cf0652102993b1 Original-Change-Id: I1eb5fd9fa6b2ae56833f024bcd3c250147bcc7a1 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376928 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16577 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20checkpatch.pl: ignore '#define asmlinkage'Martin Roth
checkpatch warns that the asmlinkage storage class should be at the beginning of the declaration when we define it to be an empty value. Change-Id: I12292d5b42bf6da9130bb969ebe00fca8efcf049 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16358 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20lint/lint-007-checkpatch: Update lint scriptMartin Roth
- Check Kconfig files as well. - Accept a list of directories to check as a command line argument. - Only look at src & util directories by default. - Skip src/vendorcode. - Remove bypass of payloads/coreinfo/util/kconfig directory, it no longer exists. Change-Id: Ia522d3ddc29914220bdaae36ea23ded7338c48fd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16623 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-20northbridge/intel/e7505/debug.c: Improve code formattingElyes HAOUAS
Change-Id: I63f58d95fa01b1f73f3620a5d13f21ef62e2404c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Makefile: Give .ali files an empty recipeNico Huber
For Ada sources, .ali files are emitted together with their respective .o files during compilation. To convince `make` that an .ali was updated when the .o was rebuilt, it needs an empty recipe. Change-Id: Ie47122ff3d00460600ed1db97362abf68f59b751 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16639 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/a-trend - emulation: Add space around operatorsElyes HAOUAS
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-20northbridge/intel/i3100: Add space around operatorsElyes HAOUAS
Change-Id: I5ff894f23dc2a2c59bc5e5d1de4287a6b9c9922c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i945: Add space around operatorsElyes HAOUAS
Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/agesa: Improve code formattingElyes HAOUAS
Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7505: Improve code formattingElyes HAOUAS
Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/superio: Add space around operatorsElyes HAOUAS
Change-Id: Ibeab5e7fe0a9005e96934b3b43cfb247ef2e2340 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20src/include: Add space around operatorsElyes HAOUAS
Change-Id: I0ee4c443b6861018f05cfc32135d632fd4996029 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16614 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-20northbridge/intel/i82830: Add space around operatorsElyes HAOUAS
Change-Id: Ic4e287209cc45fae574e7af9d45b8a0e648ef686 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/haswell: Add space around operatorsElyes HAOUAS
Change-Id: I8fa1e39bfd950475e3b55d6debcbfd92615aa379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16628 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7501: Add space around operatorsElyes HAOUAS
Change-Id: I53aa17076135e55665f2f7c6ede217388fc50cca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_rangeley: Add space around operatorsElyes HAOUAS
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20southbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: Ib48c98bb161b92b28497df26fcfd0eae2c6829df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_sandybridge: Add space around operatorsElyes HAOUAS
Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/gm45: Add space around operatorsElyes HAOUAS
Change-Id: I3781c36a3f354bfd54d20488b95d4f2307c3bce2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16629 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20southbridge/amd: Add space around operatorsElyes HAOUAS
Change-Id: I949ff7de072e5e0753d9c8ff0bf98abfca25798b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19Revert "drivers/i2c/tpm: Move common variables to header"Duncan Laurie
This reverts commit 64df72e8e2d1c086705325533767ca5e201e842a.
2016-09-19Revert "drivers/i2c/tpm: Split cr50 driver from main driver"Duncan Laurie
This reverts commit c565f9910707b91fcc7a27bab28806e558bb474d.
2016-09-19Revert "drivers/i2c/tpm/cr50: Reduce max buffer size"Duncan Laurie
This reverts commit 97a2a1ece152b6d40a524361721405b77c37959d.
2016-09-19Revert "drivers/i2c/tpm/cr50: Clean up timeouts"Duncan Laurie
This reverts commit 93c778688f0bf2f90334505a3082a2cd4ce1623a.
2016-09-19Revert "drivers/i2c/tpm/cr50: Rename i2c read/write functions"Duncan Laurie
This reverts commit 6f5ceb26b9b3e1455ebbd6192e1d2c832bddc77e.
2016-09-19Revert "drivers/i2c/tpm/cr50: Clean up locality functions"Duncan Laurie
This reverts commit 557e1a729a9ca89e814220b6203b7ac0dc446913.
2016-09-19Revert "drivers/i2c/tpm/cr50: Improve data handling and function names"Duncan Laurie
This reverts commit 1241e7db55aff313e56bf4546d969c11368b08a2.
2016-09-19Revert "x86: acpi: Add function for querying GPE status"Duncan Laurie
This reverts commit 884dfe632940b940df68d09f997fa5cd25121def.
2016-09-19Revert "soc/intel/apollolake: Initialize GPEs in bootblock"Duncan Laurie
This reverts commit 5e3dad66227bba4be9365ee76d00231bb5577b56.
2016-09-19Revert "soc/intel/apollolake: Add function to read and clear GPE status"Duncan Laurie
This reverts commit 3d43a7c111d00be246160a04023fe438ae0cac57.
2016-09-19Revert "drivers/i2c/tpm/cr50: Support interrupts for status"Duncan Laurie
This reverts commit a5e419c51187d24818f056327746a18676fe3a20.
2016-09-19Revert "mainboard/google/reef: Enable cr50 TPM interrupt"Duncan Laurie
This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
2016-09-19mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Support interrupts for statusDuncan Laurie
Support reading the ACPI GPE status (on x86) to determine when the cr50 is ready to return response data or is done processing written data. If the interrupt is not defined by Kconfig then it will continue to use the safe delay. This was tested with reef hardware and a modified cr50 image that generates interrupts at the intended points. BUG=chrome-os-partner:53336 Change-Id: I9f78f520fd089cb4471d8826a8cfecff67398bf8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19soc/intel/apollolake: Add function to read and clear GPE statusDuncan Laurie
Implement the generic acpi_get_gpe() function to read and clear the GPE status for a specific GPE. Tested by watching GPE status in a loop while generating interrupts manually from the EC console. BUG=chrome-os-partner:53336 Change-Id: Id885e98d48c2133a868da19eca3360e2dfb82e84 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19soc/intel/apollolake: Initialize GPEs in bootblockDuncan Laurie
Initialize the GPEs from mainboard config in bootblock, so they can be used in verstage to query latched interrupt status. I still left it called in ramstage just to be sure that the configuration was not overwritten in FSP stages. Tested by reading and reporting GPE status in a loop in verstage and manually triggering an interrupt on EC console. BUG=chrome-os-partner:53336 Change-Id: I1af3e9ac1e5c59b9ebb5c6dd1599309c1f036581 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19x86: acpi: Add function for querying GPE statusDuncan Laurie
Add a function that can be implemented by the SOC to read and clear the status of a single GPE. This can be used during firmware to poll for interrupt status. BUG=chrome-os-partner:53336 Change-Id: I536c2176320fefa4c186dabcdddb55880c47fbad Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Improve data handling and function namesDuncan Laurie
Unify the function names to be consistent throughout the driver and improve the handling while waiting for data available and data expected flags from the TPM. BUG=chrome-os-partner:53336 Change-Id: I7e3912fb8d8c6ad17d1af2d2a7189bf7c0c52c8e Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Clean up locality functionsDuncan Laurie
Clean up the mask and timeout handling in the locality functions that were copied from the original driver. BUG=chrome-os-partner:53336 Change-Id: Ifa1445224b475aec38c2ac56e15cb7ba7fcd21ea Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Rename i2c read/write functionsDuncan Laurie
Rename the low-level functions from iic_tpm_read/write to cr50_i2c_read/write to better match the driver name, and pass in the tpm_chip structure to the low-level read/write functions as it will be needed in future changes. BUG=chrome-os-partner:53336 Change-Id: Ib4a68ce1b3a83ea7c4bcefb9c6f002f6dd4aac1f Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Clean up timeoutsDuncan Laurie
Use two different timeouts in the driver. The 2ms timeout is needed to be safe for cr50 to cover the extended timeout that is seen with some commands. The other at 2 seconds which is a TPM spec timeout. BUG=chrome-os-partner:53336 Change-Id: I77fdd7ea646b8b2fef449f07e3a08bcce174fe8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm/cr50: Reduce max buffer sizeDuncan Laurie
Reduce the static buffer size from the generic default 1260 down to 64 to match the max FIFO size for the cr50 hardware and reduce the footprint of the driver. BUG=chrome-os-partner:53336 Change-Id: Ia88facca607f3fd5072d0d986323fde075f15855 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm: Split cr50 driver from main driverDuncan Laurie
Originally I thought it would be cleaner to keep this code in one place, but as things continue to diverge it ends up being easier to split this into its own driver. This way the different drivers in coreboot, depthcharge, and the kernel, can all be standalone and if one is changed it is easier to modify the others. This change splits out the cr50 driver and brings along the basic elements from the existing driver with no real change in functionality. The following commits will modify the code to make it consistent so it can all be shared with depthcharge and the linux kernel drivers. BUG=chrome-os-partner:53336 Change-Id: Ia9a65e72519b95f5739e3b7a16b9c2431d64ebe2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19drivers/i2c/tpm: Move common variables to headerDuncan Laurie
Move the common enums and variables to tpm.h so it can be used by multiple drivers. BUG=chrome-os-partner:53336 Change-Id: I0febe98620d0ddd4ec6b46cd3073e48c12926266 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-20gru: Add USB 2.0 PHY tuning for KevinJulius Werner
This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/370900 Original-Reviewed-by: Guenter Roeck <groeck@chromium.org> Original-Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://review.coreboot.org/16265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19soc/intel/skylake: Add FSP 2.0 support in ramstageNaresh G Solanki
Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19driver/intel/fsp1_1: Utilise soc/intel/common for adding vbt.binNaresh G Solanki
Remove fsp1.1 driver code that adds vbt.bin & use soc/intel/common instead to add vbt.bin in cbfs. Also, VBT blob is added to CBFS as RAW type hence when walking the CBFS to find vbt.bin, search with type as RAW. Change-Id: I08f2556a34f83a0ea2b67b003e51dcace994361b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16610 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19mainboard/google/reef: Configure WLAN as wake sourceVaibhav Shankar
This implements PRW method for WLAN and configures PCIe wake pin to generate SCI. BUG=chrome-os-partner:56483 TEST=Suspend the system into S3 or S0ix. System should resume through wake event from wifi. Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16611 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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