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2018-01-25cpu/x86: don't utilize UDELAY_IO if GENERIC_UDELAYAaron Durbin
If GENERIC_UDELAY is selected don't try to use UDELAY_IO as there will be a udelay() conflict at link time. BUG=b:72378235,b:72170796 Change-Id: I9e01c9daddd0629ecc38a809889b39a505c0e203 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25lib: include timer.c for all stages for GENERIC_UDELAYAaron Durbin
In order to fully utilize GENERIC_UDELAY in smm and postcar the udelay() implementation needs to be included. Do that. BUG=b:72378235,b:72170796 Change-Id: Ia20c1ed41ee439bb079e00fb7bd9c1855e31e349 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25mb/google/kahlee: Add Grunt touchscreen supportJustin TerAvest
This commit adds support for an Elan touchscreen device connected over I2C via devicetree. BUG=b:72121803 TEST=Confirm the device is probed for. Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25mb/google/kahlee: Add Grunt devicetree i2c bus cfgJustin TerAvest
I2C bus configuration is generally set up in devicetree.cb. This change establishes listings for the buses so that they can be used (though followup changes should update the buses to have correct timings). BUG=b:72121803 Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Select DRIVERS_I2C_GENERICJustin TerAvest
This is required to add support for I2C devices on Kahlee to ACPI tables via devicetree.cb. Without this, operations are not emitted for I2C devices and the proper ACPI table entries are not generated. BUG=b:72121803 Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-25soc/amd/stoneyridge: Add I2C devicetree support.Justin TerAvest
This commit establishes the stoneyridge implementation for i2c entries in the devicetree.cb file. BUG=b:72121803 Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25src/amd/stoneyridge: Add devicetree ACPI namesJustin TerAvest
This commit adds device name to ACPI name bindings for various entries in the devicetree. BUG=b:72121803 Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/kahlee: Correct grunt HWID in GBBJustin TerAvest
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296 comes from the lower four numbers from running: $ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST')) BUG=b:72436450 Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23411 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25sconfig: Add a new mmio resource typeJustin TerAvest
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25src/soc/amd/stoneyridge/Kconfig: Use vbios new locationRichard Spiegel
3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated to use VBIOS.bin new location. BUG=b:70785272 TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it should work (need to rebuild .config first). CQ-DEPEND=CL:881709 Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-25soc/intel/skylake: Clean up the skylake PCH H device ID macrosV Sowmya
Rename the device ID macros as per the skylake PCH H external design specification. Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23381 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25mb/google/poppy/variants/nami: Disable SATAKane Chen
This change disables SATA controller in order to make SATA IP enter low power status. BUG=b:72332817 TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status and verify SATA IP enters low power state Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23354 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25mb/intel/glkrvp: Select SOC_ESPI to enable eSPIShaunak Saha
Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC and enable eSPI instead. TEST=Boot to OS Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-25soc/intel/cannonlake: enable pch link in bootblockCaveh Jalali
This moves the call to pch_enable_lpc() from romstage to bootblock. In other words, it happens earlier in the boot process. Turns out, we need this to talk to the EC to determine if we're in recovery mode or not. BUG=b:69011806 TEST=boots to linux Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25mainboard/google/zoombini: add ACPI entry for cr50Caveh Jalali
This adds coreboot device tree entries on zoombini & meowth for the cr50. Also, fixes the GPIO pin IRQ settings to be falling edge. This is based on what we do for fizz. BUG=b:71722449 TEST=booted to linux on meowth: tpm_version command now sees the cr50. localhost ~ # tpm_version TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 localhost ~ # uname -a Linux localhost 4.14.13 #3 SMP PREEMPT Sat Jan 13 02:55:45 PST 2018 x86_64 Genuine Intel(R) CPU 0000 @ 1.00GHz GenuineIntel GNU/Linux localhost ~ # and we see interrupts when talking to the cr50: localhost ~ # grep cr50 /proc/interrupts ; tpm_version ; grep cr50 /proc/interru pts 84: 4687 IO-APIC 84-edge cr50_spi TPM 2.0 Version Info: Chip Version: 2.0.0.0 Spec Family: 322e3000 Spec Family String: 2.0 Spec Level: 0 Spec Revision: 116 Manufacturer Info: 43524f53 Manufacturer String: CROS Vendor ID: xCG fTPM TPM Model: 00000001 Firmware Version: 0ad551830bcf7a82 84: 4799 IO-APIC 84-edge cr50_spi localhost ~ # Change-Id: I9d503334502503ef49515e4a8736d967bc454a98 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-25mb/google/poppy/variants/nami: Enable elan touchpad wakeup system from S3/S0ixVan Chen
BUG=b:71839089 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. powerd_dbus_suspend 3. touch touchpad to wakeup system 4. localhost ~ # cat /var/log/eventlog.txt | 2018-01-21 17:01:59 | S0ix Enter | 2018-01-21 17:02:04 | S0ix Exit | 2018-01-21 17:02:04 | Wake Source | GPIO | 80 Change-Id: Ie550cfa3f7b5fd105f89c16076d428743392d0e4 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23363 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25soc/intel/skylake: Send correct ddr_type to SMBIOS TableBarnali Sarkar
The FSP 2.0 Memory_Info_HOB for KBL is not sending "MemoryType" value as what is required for SMBIOS Table according to SMBIOS Spec. Thus, converting the value retrieved from FSP HOB to the correct value. This change will not be required for upcoming SOCs since FSP have fixed this issue in its next platforms and thus it will take care and send the correct value in "MemoryType" field based on SMBIOS spec. Thus this conversion from coreboot will not be required in the next platfoms. "MemoryType" value can be directly passed to dimm_info_fill() function. BUG=none BRANCH=none TEST=Tested in Soraka, and getting the value as 0x1D for LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17 will also show correct information. Currently, it was showing "Unknown". Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-24payloads/nvramcui/payload.sh: Fix shellcheck warningsMartin Roth
In payloads/nvramcui/payload.sh line 5: DIR=`dirname $0` ^-- SC2006: Use $(..) instead of deprecated `..` ^-- SC2086: Double quote to prevent globbing and word \ splitting. In payloads/nvramcui/payload.sh line 6: lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1 ^-- SC2086: Double quote to prevent globbing and word \ splitting. ^-- SC2086: Double quote to prevent \ globbing and word splitting. ^-- SC2069: The order of \ of the 2>&1 and the \ redirect matters. The \ 2>&1 has to be last. Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24soc/amd/stoneyridge/spi: do not open code existing CAR APIsAaron Durbin
The CAR APIs already exist to deal with proper type useage. Don't open code things that already exist. BUG=b:65485690 Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-24mainboard/intel/cannonlake_rvp: remove redundant settingLijian Zhao
Clean up the extra DRIVERS_I2C_GENERIC BUG=None TEST=None Change-Id: Ida32b6f99c40c022aa8548f7353abf1d60ba4ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24util/docker/coreboot-sdk: Add msitools & rsyncMartin Roth
- The em100 project needs msitools. - Flashrom uses rsync. Change-Id: Ie01064adede25471a860bc22c0a59b31202b56c2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24soc/amd/stoneyridge: provide alternate monotonic timerAaron Durbin
The TSC has been observed to be ticking at a non-constant rate in early boot. The root cause is still not known, but this misbehavior necessitates an alternative monotonic timer source. Use the perf TSC which ticks at 100 MHz. This also means the timestamp table is not accurate as well. Root cause of TSC rate instability needs to be resolved in order to fix that. BUG=b:72170796 Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-24util/amdfwtool/amdfwtool.c: Verify it actually read bytesRichard Spiegel
The function read() returns the number of bytes actually read. Program is assuming it actually read the required number of bytes without checking. This is wrong. This fixes CIDs 1353019 and 1353021 BUG=b:72062481 TEST=Build no errors Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24soc/intel/cannonlake: Add child CARD device into eMMC/SD controllerSubrata Banik
For the internal eMMC to be used by non-chrome for installation, the CARD device and _RMV methods are required. Without these, other OSes does not show the eMMC as a valid installation target. TEST= boot CNL-RVP with Tiano payload and install Windows 10 to the internal eMMC drive. Change-Id: Icfdccd88bc113d97c2fabf4c63d8d772737a6057 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24soc/intel/cannonlake: Port SD Controller W/A from Intel Reference codeSubrata Banik
Solution: To do an additional config read to the SD controller after the controller has been power gated (put to D3) Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference codeSubrata Banik
Solution: To do an additional config read to the eMMC controller after the controller has been power gated (put to D3) Change-Id: Ieac939c9108e84ba6c7c26b1a49aaf829d8456b7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-24drives/i2c/designware: incorporate device_operations supportAaron Durbin
In ramstage the device_operations are needed for the i2c designware host controller. Move the intel/common/block/i2c implementation into the generic driver so other platforms can take advantage of it. BUG=b:72121803 Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-24drivers/i2c/designware: namespace soc functionsAaron Durbin
Rename the following functions to ensure it's clear that the designware i2c host controller driver is the one that these functions are associated with: i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg() i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base() i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus() i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn() BUG=b:72121803 Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23371 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24device/i2c_bus: allow i2c_bus and i2c_simple to coexistAaron Durbin
If one wants to implement both i2c_bus.h and i2c_simple.h APIs the compilation unit needs to be guarded or coordinated carefully with different compilation units. Instead, name the i2c_bus functions with _dev such that it indicates that they operate on struct device. One other change to allow i2c_bus.h to be built in non-ramstage environments is to ensure DEVTREE_CONST is used for the dev field in struct bus. BUG=b:72121803 Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24AGESA f15 cimx/sb700: Remove vendorcode sourceKyösti Mälkki
Change-Id: If5a72786d1119908073488c1d6d8787ac0f4f95c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24AGESA f15 cimx/sb700: Remove unused chips codeKyösti Mälkki
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24amd/torpedo cimx/sb900: Fix include directoryKyösti Mälkki
Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24mb/google/fizz: Add AC/DC loadline settingsGaggery Tsai
This patch adds AC and DC loadline settings since vr_config_enable is set. Without correct AD/DC loadline settings, VRs reported incorrect VID values which caused CPU freqency clipping. The clipping reason could be retrieved from MSR 0x64F. From VRTT report, the AC/DC loadline resistances are within spec, we can use default value defined in Table 6-1, doc #543977. BUG=b:70646304 BRANCH=None TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline settings from DCI to ensure the values were programmed correctly. Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23349 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23mainboard/glkrvp: Ignore DMIC_DATA pin IOSSTATERavi Sarawadi
Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice. By doing this, SoC can see the DMIC DATA and use for WoV processing. Thus configuring GPIO_173 as IGNORE IOSSTATE. TEST=put DUT in S0ix, verify DUT wakes up Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23246 Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23payloads/depthcharge: Update stable version upstream masterMartin Roth
Updating from commit id f3bb31fee: 2017-09-08 (vboot: Support EC early firmware selection) to commit 61cfcc3b: 2018-01-17 (meowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2) This brings in 57 new commits. Change-Id: Iadacc6017abbcc659e461d2fc27990ef8124871b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23Update vboot submodule to upstream masterMartin Roth
Updating from commit id f6780a36: 2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge) to commit id e0b38418: 2018-01-16 04:08:26 -0800 - (image_signing: Add sha1sum of keys in keyset to VERSION.signer.) This brings in 25 new commits. Change-Id: If60f19decd91eaafec1d555c1e7d3ca0249d8068 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23Update arm-trusted-firmware submodule to upstream masterMartin Roth
Updating from commit id b1187232: 2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons) to commit id 9fd4a36c: 2018-01-17 17:34:29 +0000 - (Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state) This brings in 596 new commits. Change-Id: Icbe7ede1583f715f3e30bf013df6ba164319e3a1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-23util/amdfwtool/amdfwtool.c: Check for negative returnRichard Spiegel
File open function <open()> will return -1 if there's any error. Check that the return is greater or equal to 0 before using fstat(). Print error message and exit if there's an error. This fixes CIDs 1353018, 1353020, 1353027 and 1353028 BUG=b:72062481 TEST=Build no errors Change-Id: I77d6973d1ad1eadb93922866e618038045be5937 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mainboard/google/fizz: Tune audio i2c parametersShelley Chen
Tune I2C params for I2C bus 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio <= 400MHz Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23grunt: Enable TPMChris Ching
Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create the appropriate selection based on selected board, and if grunt then define the I2C address. BUG=b:69416132 BRANCH=none TEST=make all Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22960 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mb/google/reef,sand: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23google/kahlee/BiosCallOuts.c: Remove platform_FchParams_resetRichard Spiegel
Function platform_FchParams_reset() is now an empty function, remove it, its header declaration and its use. BUG=b:64140392 TEST=Build kahlee. Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO tableRichard Spiegel
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data from agesa_board_gpios[], wrap format and delete agesa_board_gpios[]. Finally, make platform_FchParams_reset() an empty function. BUG=b:64140392 TEST=Build gardenia. Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO tableRichard Spiegel
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[] with data from agesa_board_gpios[], wrap format and delete agesa_board_gpios[] and get_gpio_table(). Then remove the get_gpio_table() call from BiosCallOuts.c. Finally, remove get_gpio_table() from google/kahlee/variants/baseboard/include/baseboard/variants.h. BUG=b:64140392 TEST=Build grunt. Build and boot kahlee, recording serial output. Search for "stage bootblock" and "stage ramstage", indicating GPIO being programmed. Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23soc/amd/stoneyridge: Add new function sb_program_gpio()Richard Spiegel
Add new function sb_program_gpio to be called after AGESA init_reset and some point within ramstage. For AGESA init_reset, change amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init (add the function after the call to AGESA function). BUG=b:64140392 TEST=Build kahlee, grunt, gardenia. Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22987 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23soc/amd/stoneyridge/southbridge.c: Create a GPIO programming functionRichard Spiegel
Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee, grunt and gardenia to be able to test a build. BUG=b:64140392 TEST=Build kahlee, grunt and gardenia with GPIO programming call at bootblock. This call is removed before commit, so bootblock.c is not committed. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-23mb/google/poppy/variants/nami: Remove iccmax setting from devicetreeFurquan Shaikh
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings) provides correct iccmax settings for kbl-u based on the SKU. Thus, there is no need to override these values in devicetree. This change gets rid of iccmax settings in the nami devicetree. Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-23src/soc/intel/cannonlake: Update C-state latency control limitsVaibhav Shankar
PC10 is a necessary condition for S0ix entry. With the current C-state limits, CPU fails to enter PC10 during S0ix. C-state Latency control limits have to be tuned to new values for PC10 entry. Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/23220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23util/lint: Unify checks for git worktreeAlex Thiessen
Linters try to determine whether they are running in a git worktree so that `git grep` can be used instead of `grep`. These checks are done in different not truly correct ways and thus the linters don't use `git grep` when running from a worktree subdirectory, e.g. in a git subtree environment. Unify checks using `git rev-parse --is-inside-work-tree`. Change-Id: I3f54afc99ad0f0e3052cffdd32bdd9649cf3d720 Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/23297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 10:34:35 +0000