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2017-06-16purism/librem13v2: Add Kconfig defaultsYouness Alaoui
Add default values for MAINBOARD_VERSION and CBFS_SIZE. Change-Id: Ib6461cef78f3fea448baf1ada456e3c8335f1543 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-16purism/librem13v2: Clean up devicetreeMatt DeVillier
- remove unused I2C, serialIO defs - set PL2 override, VR mailbox cmd based on SKL-U ref board, as values copied from google/chell are for SKL-Y Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16purism/librem13v2: Update USB configMatt DeVillier
Update devicetree USB config based on board spec. Leave OC pins set to skip since the info is unavailable. Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16soc/intel/braswell: Hide some Kconfig options in menuconfigArthur Heymans
Don't allow the user to set PCIe configspace base address. Don't allow the user to set the DCACHE size and base. Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16soc/intel/skylake: Don't allow user to change DCACHE base and sizeArthur Heymans
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16src/soc/intel: Don't allow user to select PCIe config mmio sizeArthur Heymans
Change-Id: I8b2794f56f39492589a08e5676cb33eec89a976e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20179 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16src/soc/intel/common: Don't allow user to change PCIe BARArthur Heymans
Change-Id: I254549057552be93611afa8ca52d22be220fe3dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16soc/intel/apollolake: Removing some menuconfig optionsArthur Heymans
Does not need to changeable in menuconfig. Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-16sb/intel/common/firmware: Keep CHECK_ME disabled by defaultNaresh G Solanki
While building poppy board, build failed with following error message: Writing new image to build/coreboot.pre.new mv build/coreboot.pre.new build/coreboot.pre util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null This image does not contains a ME/TXE firmware NR = 0) make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55: add_intel_firmware] Error 1 Hence keeping CHECK_ME unset by default. TEST=Succesfully built coreboot for Poppy & booted to OS. Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-16google/slippy: Don't force native graphics initPatrick Georgi
The board dutifully registers an int15h handler and provides the defaults to add a VGABIOS. That should be good enough to initialize graphics through the VGABIOS file. Fixes build on Chrome OS configurations (at least until the Ada toolchain situation is resolved over there). Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-06-15google/gru: drive the stronger pull-up for touchpadCaesar Wang
As the hardware designed on gru, the AP_I2C_TP_PU_EN (gpio3_b4) controlled the SCL/SDA status to avoid leakage. And the gpio3_b4 of rk3399 pull resistor is 26k~71k and 3.3v for supply power, and gpio3_b4 pin connected 2.2k resistor to i2c of TP device. The default of this gpio status is pulled up during the start to bootup, it's very weak drive for the TP device that maybe cause to trigger the recovery process of elan's firmware. Also, the Elan updated its firmware(102.0.5.0) to delay checking the i2c of touchpad is greater than 1 second. So we have to drive the stronger pull-up within 1 second of powering up the touchpad to prevent its firmware from falling into recovery. Change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-06-15nb/intel/haswell/gma: Use common init_igd_opregion methodPatrick Rudolph
Use common init_igd_opregion method and remove duplicated code in acpi.c. Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-15nb/intel/haswell/gma: Write ACPI tablesPatrick Rudolph
Add method gma_write_acpi_tables. No need to update GNVS as it doesn't have ASLB. Change-Id: Ia138cfde2271a298c36b85e999ff69f0f211ba11 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-15Revert "sb/intel/bd82x6x: Disable unused bridges"Nico Huber
This reverts commit f4835a85c0e851d13bcfed53a23f495caeefe8e2. It completely ignores port coalescing and breaks enumeration in many cases. The code reused to disable and hide the root ports was never meant to be called that way. The same effect of power saving can likely be achieved by clock gating unused ports after enumeration without further, error-prone function hiding. Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-15drivers/xgi: Fix usage of NGI Kconfig optionsNico Huber
This driver reinvented MAINBOARD_DO_NATIVE_VGA_INIT in a very special way: If it wasn't set, perform native gfx init in textmode, if it was set, perform native gfx init in linear framebuffer mode. Test for LINEAR_FRAMEBUFFER instead and make the native gfx init optional. Also, make Kconfig reflect the actual behaviour. Change-Id: If20fd1f5b0f4127b426e8ff94acc61fcd4eb49af Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-15nb/via/cn700: Guard VGA_BIOS_ID appropriatelyNico Huber
This was the single spot where VGA_BIOS_ID wasn't guarded by anything. It resulted in the wrong default id if we didn't chose to add a VGA BIOS at first but added one later (e.g. a board provided default guarded by VGA_BIOS wasn't applied then, because the Via/CN700 value was already set). Change-Id: Ia16a5e6d194191d8da8c551d6eb3849bc65864a9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-15soc/intel/apollolake: revert CPU MP init prior to FSP-SAaron Durbin
A major regression was introduced with commit 6520e01a (soc/intel/apollolake: Perform CPU MP Init before FSP-S Init) where the APs execution context is taken away by FSP-S. It appears that FSP-S is not honoring the SkipMpInit UPD because it's been shown with some debug code that FSP-S is compeltely hijacking the APs: Chrome EC: Set WAKE mask to 0x00000000 Chrome EC: Set WAKE mask to 0x00000000 CBFS: 'VBOOT' located CBFS at [440000:524140) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 2e700 size 1a00 Running FSPS in 4 secs.. 315875 4315875 cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work cpu2 Waiting for work cpu3 Waiting for work cpu1 Waiting for work Running FSPS.. 4315875 4315875 ITSS IRQ Polarities Before: ITSS IRQ Polarities Before: IPC0: 0xffffeef8 IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0x00ffffff ITSS IRQ Polarities After: IPC0: 0xffffeef8 IPC1: 0x4a07ffff IPC2: 0x08000000 IPC3: 0x00a11000 This is essentially a revert of 6520e01a to fix the previous behavior. Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2017-06-15nb/intel/sandybridge/gma: Use common init_igd_opregion methodPatrick Rudolph
Use common init_igd_opregion method. Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15nb/intel/nehalem/gma: Use common init_igd_opregion methodPatrick Rudolph
Use common init_igd_opregion method. Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15nb/intel/gm45: Don't allow too low values for gfx_uma_sizeArthur Heymans
Too low gfx_uma_size can result in problems if the framebuffer does not fit. This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes from cmos" Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-14drivers/fsp1_1: decouple VBT from execution of GOP driverMatt DeVillier
Commit 2e7f6cc introduced the 'no graphics init' option for FSP 1.1 SoCs using a GOP driver to init the display, but selecting that option while including a VBT breaks compilation for Braswell and Skylake devices because the VBT and GOP driver are intertwined. This patch decouples the VBT from the GOP driver execution, allowing the 'no graphics init' option to compile (and work) properly when CONFIG_ADD_VBT_DATA_FILE=y. Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20210 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-14mainboard/google/{poppy,soraka}: Disable unused GSPI1 interfaceFurquan Shaikh
TEST=Verified that board still boots to OS without any error. Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-14mainboard/google/{poppy,soraka}: Enable generation of SPI TPM ACPI nodeFurquan Shaikh
Now that we dynamically disable TPM interface based on config options, add support for generation of SPI TPM ACPI node if SPI TPM is used. Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-14mainboard/google/poppy: Disable unused TPM interface dynamicallyFurquan Shaikh
Based on the config options selected, decide at runtime which TPM interface should be disabled so that ACPI tables are not generated for that interface. TEST=Verified that unused interface does not show up in ACPI tables. Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20141 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14soc/intel/skylake: Add missing PCH_DEV_* definitionsFurquan Shaikh
Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-14soc/intel/common/block/i2c: Ignore disabled I2C devicesFurquan Shaikh
If I2C device is disabled: 1. BAR for the device will be 0 2. There is no need to generate ACPI tables for the device TEST=Verified that if an i2c device is disabled statically in devicetree or dynamically in mainboard, then coreboot does not die looking for missing resources. Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14Add support for Undefined Behavior SanitizerRyan Salsamendi
Initial support for undefined behavior sanitizer in ramstage. Enabling this will add -fsanitize=undefined to the compiler command line and link with ubsan.c in ramstage. Code with UB triggers a report with error, file, and line number, then aborts. Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-14cbmem_console: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Left shifting an int where the right operand is >= width of type is undefined. Add ul suffix since it's safe for unsigned types. Change-Id: I4b2365428e421085285006bc1ea8aea75890ff65 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-14arch/x86: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that is not aligned to the size of access is undefined behavior. Switch to memcpy() for unaligned write to EBDA_LOWMEM. Change other write16()s in setup_ebda() to memcpy() for consistency. Change-Id: I79814bd47a14ec59d84068b11d094dc2531995d9 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14inteltool/Makefile: Clean .dependencies tooNico Huber
Change-Id: Ib4fc326c6612f2d142c8a5220949fbb4b97c37a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-14inteltool/Makefile: Separate CPPFLAGS from CFLAGSNico Huber
Separate the required CPPFLAGS from environment overridable CFLAGS. Change-Id: I0c1c0a1cebc7f7971634bf57d4a2370939c43fda Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-14cbmem: Escape literal asterisks in log banner regexJulius Werner
I had a stupid. :( Asterisks have a special meaning in regexes, but I just wanted to match three literal ones. This kills the regex parser. Change-Id: Ia6149e72715d651c914583ed3235680ce5b7a2e0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-14soc/intel/skylake: Add USB port number information to wake sourceFurquan Shaikh
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-13nb/intel/pineview/raminit.c: Use static const for lookup tablesArthur Heymans
Also changes the arguments of some functions to const. This reduces romstage size by a whopping 1009 bytes. Change-Id: I054504412524b7be19d98081097843b61bc0c459 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-13cpu/x86/mtrr: fail early if solution exceeds available MTRRsAaron Durbin
If an MTRR solution exceeds the number of available MTRRs don't attempt to commit the result. It will just GP fault with the MSR write to an invalid MSR address. Change-Id: I5c4912d5244526544c299c3953bca1bf884b34d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20163 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-13cpu/amd/fam10/ram_calc: Remove superfluous guardArthur Heymans
AMD_FAM10H code enables early cbmem by default. Change-Id: Ifad007f6604bb612d544cf1387938a8fef1cceb4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-13siemens/mc_apl1: Enable decoding for COM 3 on LPCMario Scheithauer
Since this mainboard provides 3 COM ports on LPC, enable decoding of the corresponding address range for COM 3. Change-Id: I15c0748fce67eef46401c314f441aa45f5e3c5fa Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-06-13device/pnp: remove struct io_infoSamuel Holland
The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Myles Watson <mylesgw@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-13siemens/mc_apl1: Use Siemens NC FPGA driverMario Scheithauer
- use Siemens NC FPGA driver for backlight brightness and PWM control - set Dsave time for board reset after falling edge of signal xdsave Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-13siemens/nc_fpga: Expand FPGA functionalityMario Scheithauer
The siemens/mc_apl1 mainboard needs more functionality provided by Siemens NC FPGA. The additional functionality contains backlight brightness/PWM control and Dsave time for board reset. Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-13vendorcode/siemens: Add new values to hwilibMario Scheithauer
The Siemens mc_apl1 mainboard needs new values from hwilib. - add Dsave time for board reset - add backlight brightness for panel setting - add backlight PWM period Change-Id: I3a48654ef57c7f8accaabe60e8aec144e4fe5466 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12MAINTAINERS: Add Julius as ARM architecture maintainerJulius Werner
I'm pretty much already doing this anyway, so I might as well document it. Separating out some older ARM SoCs that were added by other people and are pretty much orphaned now. I can also fill out the MISSING: MEMLAYOUT point (since I wrote that). Change-Id: I8b78d592a1ed68a42e5785ebdc13df2edf9007bf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-12nb/intel/gm45: Add romstage timestampsArthur Heymans
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12nb/intel/ivybridge: Improve CAS freq selectionArthur Heymans
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12nb/intel/sandybridge: Improve CAS freq selectionArthur Heymans
The previous code seemed weird and tried to check if its selected value is supported three times. This also lower the clock if a selected frequency does not result in a supported CAS number. Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-06-12src/cpu/amd/model_fxx/powernow_api.c Fix checkpatch errors + warningsEvelyn Huang
Fix line over 80 characters, spaces required around comparisons,space required after close brace '}', comma ',', semicolon ';', space prohibited after ')' errors and warnings Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-12mb/foxconn/g41s-k: add new mainboardSamuel Holland
Based on the Intel G41 chipset, ICH7 southbridge, and IT8720F Super I/O. Tested, working: * Booting Linux 4.11.3 and Windows 8.1 from USB and HDD * Resume from S3 (Linux and Windows) * Native raminit (DDR2-800) * Native graphics init (SeaBIOS, Linux) * Graphics init with VGA BIOS (SeaBIOS, Windows) * PCI-E x16 PEG slot, PCI-E x1 slot from southbridge * Realtek ALC888 HD Audio (including front panel and jack detection) * Realtek R8168 Gigabit LAN * Both SATA ports * USB 1.1 and 2.0 devices (keyboard, mass storage) * PC speaker beep * COM header * Super I/O Environment controller (temps, voltage, fans) * PS/2 keyboard and mouse * Flashing with `flashrom -p internal` * 1MiB and 2MiB SPI flash chips * CMOS gfx_uma_size Appears, OS driver loads, but otherwise untested: * IrDA header * CIR header * TPM header Untested: * S/PDIF digital audio Tested, known broken: * CMOS power_on_after_fail * USB keyboard in secondary payloads Change-Id: Ifc4c8935b1a11e55f4bf6cfa484a8a8d09b1adda Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20027 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-12ec/librem/ec: Fix offset for Bluetooth enable (BTLE)Matt DeVillier
Test: boot OS (Ubuntu, Windows 10) on librem13v2, verify BT function key toggle now works correctly. Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-12mb/emulation/spike-riscv: Update UART addressJonathan Neuschäfer
I updated my spike patch[1] to cleanly apply to current spike master. As a side effect, the UART is now at 0x02100000. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I4cb09014619e230011486fa57636abe183baa4be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/20126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 15:59:33 +0000