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2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payloadPaul Menzel
If the user selects GRUB 2 as the payload in Kconfig, coreboot does not need to initialize the PS/2 keyboard as GRUB 2 is going to do it. Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payloadPaul Menzel
As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is able to initialize the PS/2 keyboard itself, so it is not necessary to let coreboot do it. SeaBIOS is also able to do it faster as discussed in a thread on the coreboot mailing list from October 2010 [1]. In that thread it was also proposed to not let coreboot initialize the PS/2 coreboot when SeaBIOS is used as a payload. [1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310 subject: [coreboot] coreboot+seabios timings Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboardPaul Menzel
Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02qemu-armv7: Kconfig cleanupKyösti Mälkki
RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7. Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02asrock/e350m1: Sanitize #includesEdward O'Callaghan
Following similar reasons as: 5ff4b08 jetway/nf81-t56n-lf: Sanitize #includes Change-Id: Ie88b884bc2d4481bc2583d5be1f4d1376547f3c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5614 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2014-05-02jetway/nf81-t56n-lf: Set OEM to Jetway in DSDT and mptablesEdward O'Callaghan
Jetway builds this hardware, so let us be sure to set the truth in the DSDT Definition block and MPTables. Change-Id: I2dfb89152aa3b895ec6975293c5a5998ab6b52bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02arch/x86/boot: Indent mpspec.c and make a loop more legibleEdward O'Callaghan
Fix some space->tab style and a for-for loop embedded to be more understandable/readable. Change-Id: I740c544e8c9330e6efbbd66a5c1e6a4a33d1a75e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5631 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02asrock/e350m1/devicetree.cb: Correctly indent device linePaul Menzel
Fix up commit dfa8a32f [1]. src/mainboard/asrock/e350m1: Properly indent devicetree.cb [1] http://review.coreboot.org/5612 Change-Id: I59b3ec2f00d69951aa8a96c4a9c3de5b219acbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5619 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cbEdward O'Callaghan
Following the reasoning in, dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5629 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02superio/winbond/w83627thg: Remove w83627thg_enable_serial symbolEdward O'Callaghan
Remove model specific implementation, w83627thg_enable_serial, from romstage component of sio support. Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5604 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02mainboard/*: Use generic winbond romstage in place of w83627thgEdward O'Callaghan
Use the generic implementation of winbond in place of the model specific w83627thg_enable_serial() as so that it maybe removed later. Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5603 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01Build without ChromeOSKyösti Mälkki
Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3978 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01ChromeOS: Use common fill_lb_gpio()Kyösti Mälkki
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01device: Conditionally bypass oprom executionKyösti Mälkki
Builds with CHROMEOS can bypass VGA oprom when boot is not in developer or recovery modes. Have the same functionality available without CHROMEOS but with BOOTMODE_STRAPS. Change-Id: I97644364305dc05aad78a744599476ccc58db163 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5595 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01ChromeOS: Remove oprom_is_loadedKyösti Mälkki
A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01google/stout: Fix build without ChromeOSKyösti Mälkki
Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01Declare recovery and developer modes outside ChromeOSKyösti Mälkki
Move the implementation for recovery and developer modes from vendorcode/google/chromes to lib/. Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01device: provide option to always load PCI option romsKyösti Mälkki
Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5594 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-04-30console: Fix UART selection promptKyösti Mälkki
Without this change, removal of default UART_FOR_CONSOLE entries under mainboard/ Kconfig will remove this option entirely from created .config file. Change-Id: I11422ddb8c51abca177f999936c995ae0c91c459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5626 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-30baytrail: Add default _OSC methodDuncan Laurie
This is needed to let the kernel know it can control everything and not to disable features. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175629 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4939 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add root bus resource regionsDuncan Laurie
Populate the PCI mmio region from NVS TOLM variable. Other regions are fixed. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175628 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4938 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add MCFG table to ACPIDuncan Laurie
This adds the PCI configuration region table to baytrail. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175627 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4937 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Clean up NVS regionDuncan Laurie
There is a lot of NVS allocated to things that are not really used. Most of these are removed and some are moved around. Thermals are expected to be handled with DPTF so I've removed that bit of code but have not yet cleaned up the thermal zone. I left in the SIO BARs since I think we will need those still even though they may need work still. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Id16ee67e6b3709a303c001afd72947147f938127 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175626 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4936 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add function to read top of low memoryDuncan Laurie
The top of low memory is also the start of the region where PCIe resources are allocated. This needs to be passed in ACPI but is only readable from IOSF. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4935 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add reserved MMIO regions to ACPIDuncan Laurie
Add a length define for all the reserved MMIO regions and use them in the ACPI code to reserve the regions there. Add a region for the "abort page" documented in the EDS. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175624 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4934 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Fix XHCI problems and re-enableDuncan Laurie
- a few clock gating bits were set improperly and were preventing the system from transitioning out of S0 state. - the XHCC registers were not getting the top byte set properly which includes things like DMA write request size and request boundary crossing control. This was causing memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot kernel from USB on rambi with XHCI driver Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4933 Tested-by: build bot (Jenkins)
2014-04-30mainboard/: Avoid including early_serial.c from w83627hfEdward O'Callaghan
Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5597 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30console: Move UART port defaults to mainboardKyösti Mälkki
Correct selection of UART depends of board layout, not the CPU internals, so default setting should originate from mainboard. Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5618 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30console: Drop EARLY_CONSOLE optionKyösti Mälkki
We have means to easily disable a specific console in romstage if necessary, so this global option makes little sense. The option was initially introduced as a work-around for build issues around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs. Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5607 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30allwinner/a10: Hide SoC specific UART functionsKyösti Mälkki
If platform has a component coreboot has to communicate with using one of the UARTs, that device would not be part of the SoC and must not use functions specific to a10 UART. Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5469 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30uart: Support multiple portsKyösti Mälkki
The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-29towiki.sh Move vendor link to the first column.Rudolf Marek
It is not easy to see that there are two links, one to coreboot wiki and second to the vendor page. This change moves the vendor page link to the vendor column, separating it nicely. Change-Id: I3063be476231d04f833350043010a6e0001697e7 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/5593 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in commentPaul Menzel
$ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g' Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5325 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29crossgcc: Support OSX 10.9 built-in tar utility program.Andrew Wu
Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in tar program is bsdtar 2.8.3. bsdtar can build crossgcc toolchain. Modify buildgcc to support tar in OSX 10.9 (uname = Darwin). Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/5598 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29src/mainboard/asrock/e350m1: Properly indent devicetree.cbEdward O'Callaghan
Trivial: clean up spaces to tabs to properly indent devicetree.cb Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5612 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29mainboard/kontron/986lcd-m: Remove a duplicate headerEdward O'Callaghan
Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5602 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29util/board_status/board_status.sh: set its executable flagPaul Menzel
Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5171 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-29AGESA SPI: Fix Kconfig optionsKyösti Mälkki
Option AMD_SB_SPI_LEN leaked to non-AMD configs. Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME. Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5606 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29SPI: Use common dependency in KconfigKyösti Mälkki
Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-28superio/winbond/w83627ehg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5589 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28mainboard/tyan/s8226: Remove redundant sio headerEdward O'Callaghan
Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/w83627dhg: Convert romstage to generic componentEdward O'Callaghan
Convert the serial init to the generic romstage component and corresponding boards using this sio. Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28mainboard/asrock/e350m1: Avoid including early_serial.cEdward O'Callaghan
Use generic winbond romstage serial init symbols instead of model specific implementation. We do this on a case by case basis as some boards are ROMCC and so need to #include .c files. This is a step to migrate non-romcc boards to a more generic superio framework. Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5591 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28superio/winbond/*: Provide common romstage componentEdward O'Callaghan
Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5587 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28AMD: Add common header file for CAR setupKyösti Mälkki
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4683 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-26superio/fintek/*: Factor out generic romstage componentEdward O'Callaghan
The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26uart8250io: Fix build with DEBUG_SMIKyösti Mälkki
Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-26libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.Edward O'Callaghan
Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5198 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-26lippert/hurricane-lx: Kconfig cleanupPatrick Georgi
A Kconfig option defined instead of selected that really comes from somewhere else. Change-Id: I8730d12ed053520b794655e943c93583c441f3f1 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5542 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 16:13:23 +0000